skywater-pdk/docs/rules/periphery/p049-hvntm_dotdash.csv

802 B

1NameDescriptionFlagsValue
2(hvntm.X.1 )Hvntm can be drawn inside HVI. Drawn layer will be OR-ed with the CL and rechecked for CLDRC
3(hvntm.1)Width of hvntmP0.700
4(hvntm.2)Spacing of hvntm to hvntmP0.700
5(hvntm.3)Min. enclosure of (n+_diff inside Hvi) but not overlapping :drc_tag:`areaid.ce` by hvntmP0.185
6(hvntm.4)Space, no overlap, between n+_diff outside Hvi and hvntmP0.185
7(hvntm.5)Space, no overlap, between p+_diff and hvntmP DE0.185
8(hvntm.6a)Space, no overlap, between p+_tap and hvntm (except along the diff-butting edge)P0.185
9(hvntm.6b)Space, no overlap, between p+_tap and hvntm along the diff-butting edgeP0.000
10(hvntm.7)hvntm must enclose ESD_nwell_tap inside hvi by atleastP0.000
11(hvntm.9)Hvntm must not overlap :drc_tag:`areaid.ce`