skywater-pdk/docs/rules/periphery/p020-dnwell_dotdash.csv

730 B

1NameDescriptionFlagsValue
2(dnwell.2)Min width of deep nwell3.000
3(dnwell.3)Min spacing between deep nwells. Rule exempt inside UHVI.6.300
4(dnwell.3a)Min spacing between deep nwells on same net inside UHVI.N/A
5(dnwell.3b)Min spacing between deep-nwells inside UHVI and deep-nwell outside UHVIN/A
6(dnwell.3c)Min spacing between deep-nwells inside UHVI and nwell outsideUHVIN/A
7(dnwell.3d)Min spacing between deep-nwells inside UHVI on different netsN/A
8(dnwell.4)Dnwell can not overlap pnp:dg
9(dnwell.5)P+_diff can not straddle Dnwell
10(dnwell.6)RF NMOS must be enclosed by deep nwell (RF FETs are listed in $DESIGN/config/tech/model_set/calibre/fixed_layout_model_map of corresponding techs)