2.5 KiB
2.5 KiB
1 | General (RES.-) | |
---|---|---|
2 | .X | Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer. |
3 | Sheet Resistance (SR.-) | |
4 | .met3 | Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology) |
5 | .met2 | Parasitic resistance is calculated for all metal2. |
6 | .met1 | Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1 |
7 | .li1 | Parasitic resistance is calculated for all li1. |
8 | .poly.1 | Parasitic resistance on gates is calculated to the center of the gate. |
9 | .poly.2 | Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model. |
10 | .diff.1 | Parasitic resistance is not extracted for any diffusion regions. |
11 | .diff.2 | Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole. |
12 | .xnwvc.1 | Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted. |
13 | contact-to-gate space (CT.-) | |
14 | .via | All vias will have parasitic resistance extracted. |
15 | .mcon | All mcons will have parasitic resistance extracted. |
16 | .licon.1 | All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted. |
17 | .licon.2 | All licons that are connnected to non-precision resistors will have resistance extracted. |
18 | .licon.3 | All licons that are connected to FETs will be extracted by RCX. |
19 | .licon.4 | All licons on diff of PNP/NPN will be considered part of the device model. |
20 | .licon.5 | All licons on tap of PNP/NPN will be considered part of the device model. |
21 | .licon.6 | All licons on non-PNP tap regions will have parasitic resistance extracted. |
22 | .hrpoly.1 | All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models. |
23 | .pwres.1 | All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models. |