skywater-pdk/docs/rules/rcx/rcx-all.csv

1	Description	Model Structure	Modeled RX		Actual CAD RX		RX Discrepancy	Modeled CX	Actual CX	CX Discrepancy
2			Contacts	Sheets	Contacts	Sheets		Sheet	Sheet
3	All Periphery FETs	mXXXX d g s b w l m ad as pd ps nrd nrs	none	diff(min)	licon/mcon/vias	diff(ext)/poly/li/m1/m2-m3	none	poly/licon/li	li/m1/m2-m3	li-negligible
4	20V NDEFETs NONISO	xXXXX d g s b w l m ad as pd ps nrd nrs	none	diff(min)/licon	mcon/vias	diff(ext)/poly/li/m1/m2-m3	none	poly/licon/li	li/m1/m2-m3	li-negligible
5	20V NDEFETs ISO	xXXXX d g s b w l m ad as pd ps nrd nrs	none	diff(min)/licon	mcon/vias	diff(ext)/poly/li/m1/m2-m3	none	poly/licon/li/dnwdiode_psub	li/m1/m2-m3	li-negligible
6	20V PDEFETs	xXXXX d g s b w l m ad as pd ps nrd nrs	none	diff(min)/licon	mcon/vias	diff(ext)/poly/li/m1/m2-m3	none	poly/licon/li	li/m1/m2-m3/dnwhvdiode_psub	li-negligible
7	Cell FETs	NOT EXTRACTED FROM LAYOUT	N/A	N/A	N/A	N/A	N/A	N/A	N/A	N/A
8	All Diodes	dXXXX n1 n2 area pj	licon	diff	licon/mcon/vias	poly/li/m1/m2-m3	licon-negligible	Junction	li/m1/m2-m3	none
9	RF ESD Diodes	xesd_XXXX n1 n2 area pj	licon/mcon/ via	li/m1/m2	via2	m3	none	li/m1/m2	m3	none
10	Parasitic PNP	qXXXX nc nb ne ns pnppar m	licon/mcon	diff/li	mcon/vias	li/m1/m2-m3	li/mcon-neglible	na	li/m1/m2-m3	none
11	Parasitic PNP (5X)	qXXXX nc nb ne ns pnppar5x m	licon/mcon	diff/li	mcon/vias	li/m1/m2-m3	li/mcon-neglible	na	li/m1/m2-m3	none
12	Parasitic NPN	qXXXX nc nb ne ns npnpar m	licon/mcon	diff/li	mcon/vias	li/m1/m2-m3	li/mcon-neglible	na	li/m1/m2-m3	none
13	Non-precision Resistors	rXXXX a b l w m	none	sheet layer	licon/mcon/vias	none (no sheet resistance where sheet layer & res id layer intersect)	none	none	junction/li/m1/m2-m3	parasitic capacitance to substrate (tool limitation)
14	Precision poly resistor	xXXXXX hrpoly_X_X r0 r1 b l w m	licon/mcon	poly/li	via	m1/m2-m3	none	poly-sub	m1/m2-m3	li-negligible
15	MIM Capacitor (2-terminal)	xXXXX xcmimc2 c0 c1 w l m	via2	m3	N/A	poly/li/m1/m2	m2 (of the device) -negligible	capm-m2	li/m1/m2-m3	routing layers underneath device
16	MIM Capacitor (3-terminal)	xXXXX xcmimc c0 c1 b w l m	via2	m3	N/A	poly/li/m1/m2	m2 (of the device) -negligible	m2-sub/capm-m2	(1) Carea of M2-sub (non-overlap CAPM w/ 0.14um upsize)\n(2) M3 Cap by 1 snap grid width	none
17	Isolated Pwell Resistor	xXXXX pwres r0 r1 b l w m	licon/mcon	pwell/li	vias	m1/m2-m3	none	none	junction/m1/m2-m3	li-negligible
18	Vertical Parallel Plate Cap	xXXXX xcmvpp c0 c1 b m (note: no special RCX implementation for VPP required since black-box LVS will be used)	mcon/via	li/m1/m2	none (black box LVS)	none (black box LVS)	none	li/mcon//m1/via/m2	none (black box LVS)	Parasitic capacitance to routing above
19	Vertical Parallel Plate Cap over MOSCAP	xXXXX xcmvpp2_* c0 c1 b m	mcon/via	li/m1/m2	none (black box LVS)	none (black box LVS)	none	li/mcon//m1/via/m2	none (black box LVS)	Parasitic capacitance to routing above
20	4-terminal Vertical Parallel Plate Cap (M3 Shielded)	xXXXXX xcmvpp*x*_m3shield c0 c1 b term4 m=	licon/mcon/ via	poly/li/m1/m2	via3/via4	m3/m4/m5	none	poly/licon/li/mcon/m1/via/m2/m3	m3-substrate (not m3-m2), neighboring metal to VPP metal	none
21	4-terminal Vertical Parallel Plate Cap (M5 Shielded)	xXXXXX xcmvpp*_*m5shield c0 c1 b term4 m=	licon/mcon/ via/via2/via3	poly/li/m1/m2/m3/m4	via4	m5	none	poly/licon/li/mcon/m1/via/m2/m3/m4/m5	neighboring metal to VPP metal	none
22	3-terminal Vertical Parallel Plate Cap	xXXXXX xcmvpp*x* c0 c1 b m=\nxXXXXX xcmvpp*x*_lishield c0 c1 b m=	mcon/ via	li/m1/m2	via2/via3/via4	m3/m4/m5	none	li/mcon/m1/via/m2	neighboring metal to VPP metal	Parasitic capacitance to routing above
23	3-terminal Vertical Parallel Plate Cap (for S8Q/S8P only)	xXXXXX xcmvpp*x*_m3_lishield c0 c1 b m=	mcon/ via/via2	li/m1/m2/m3	via3/via4	m4/m5	none	li/mcon/m1/via/m2/via2/m3	neighboring metal to VPP metal	none
24	Varactor	xXXXXX xcnwvc c0 c1 b l w m	licon/mcon/via	diff/poly/li/m1/m2	via2	m3	none	poly/li/m1/m2	nwdiodemodel/m3*	none
25	Inductor	xXXXXX xindXXXX t1 t2 body (note: no special RCX implementation for inductor required since black-box LVS will be used)	via	m2/Cu	Nothing extracted within inductor.dg layer		none	m2/via/Cu	Nothing extracted within inductor.dg layer	none