docs: Cleaning up rcx-all.csv table.
Formatted version found in [SKY130 Stackup Capacitance Data - RCX Model Information](https://docs.google.com/spreadsheets/d/1N9To-xTiA7FLfQ1SNzWKe-wMckFEXVE9WPkPPjYkaxE/edit#gid=1391862914) sheet. Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
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Tim 'mithro' Ansell
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Description,Model Structure,Modeled RX,,Actual CAD RX,,RX Discrepancy,Modeled CX,Actual CX,CX Discrepancy
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,,Contacts,Sheets,Contacts,Sheets,,Sheet,Sheet,
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All Periphery FETs,mXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min),licon/mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3,li-negligible
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20V NDEFETs NONISO,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3,li-negligible
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20V NDEFETs ISO,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li/dnwdiode_psub,li/m1/m2-m3,li-negligible
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20V PDEFETs,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3/dnwhvdiode_psub,li-negligible
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Cell FETs,NOT EXTRACTED FROM LAYOUT,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
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All Diodes,dXXXX n1 n2 area pj,licon,diff,licon/mcon/vias, poly/li/m1/m2-m3,licon-negligible,Junction,li/m1/m2-m3,none
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RF ESD Diodes,xesd_XXXX n1 n2 area pj,licon/mcon/via,li/m1/m2,via2,m3,none,li/m1/m2,m3,none
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Parasitic PNP,qXXXX nc nb ne ns pnppar m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
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Parasitic PNP (5X),qXXXX nc nb ne ns pnppar5x m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
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Parasitic NPN,qXXXX nc nb ne ns npnpar m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
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Non-precision Resistors,rXXXX a b l w m,none,sheet layer,licon/mcon/vias,none (no sheet resistance where sheet layer & res id layer intersect),none,none,junction/li/m1/m2-m3,parasitic capacitance to substrate (tool limitation)
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Precision poly resistor,xXXXXX hrpoly_X_X r0 r1 b l w m,licon/mcon,poly/li,via,m1/m2-m3,none,poly-sub,m1/m2-m3,li-negligible
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MIM Capacitor (2-terminal),xXXXX xcmimc2 c0 c1 w l m ,via2,m3,N/A,poly/li/m1/m2,m2 (of the device) -negligible,capm-m2,li/m1/m2-m3,routing layers underneath device
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MIM Capacitor (3-terminal),xXXXX xcmimc c0 c1 b w l m ,via2,m3,N/A,poly/li/m1/m2,m2 (of the device) -negligible,m2-sub/capm-m2,(1) Carea of M2-sub (non-overlap CAPM w/ 0.14um upsize)\n(2) M3 Cap by 1 snap grid width,none
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Isolated Pwell Resistor,xXXXX pwres r0 r1 b l w m,licon/mcon,pwell/li,vias,m1/m2-m3,none,none,junction/m1/m2-m3,li-negligible
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Vertical Parallel Plate Cap,xXXXX xcmvpp c0 c1 b m (note: no special RCX implementation for VPP required since black-box LVS will be used),mcon/via,li/m1/m2,none (black box LVS),none (black box LVS),none,li/mcon//m1/via/m2,none (black box LVS),Parasitic capacitance to routing above
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Vertical Parallel Plate Cap over MOSCAP,xXXXX xcmvpp2_* c0 c1 b m ,mcon/via,li/m1/m2,none (black box LVS),none (black box LVS),none,li/mcon//m1/via/m2,none (black box LVS),Parasitic capacitance to routing above
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4-terminal Vertical Parallel Plate Cap (M3 Shielded),xXXXXX xcmvpp*x*_m3shield c0 c1 b term4 m=,licon/mcon/via,poly/li/m1/m2,via3/via4,m3/m4/m5,none,poly/licon/li/mcon/m1/via/m2/m3,"m3-substrate (not m3-m2), neighboring metal to VPP metal",none
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4-terminal Vertical Parallel Plate Cap (M5 Shielded),xXXXXX xcmvpp*_*m5shield c0 c1 b term4 m=,licon/mcon/via/via2/via3,poly/li/m1/m2/m3/m4,via4,m5,none,poly/licon/li/mcon/m1/via/m2/m3/m4/m5,neighboring metal to VPP metal,none
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3-terminal Vertical Parallel Plate Cap,xXXXXX xcmvpp*x* c0 c1 b m=\nxXXXXX xcmvpp*x*_lishield c0 c1 b m=,mcon/via,li/m1/m2,via2/via3/via4,m3/m4/m5,none,li/mcon/m1/via/m2,neighboring metal to VPP metal,Parasitic capacitance to routing above
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3-terminal Vertical Parallel Plate Cap (for S8Q/S8P only),xXXXXX xcmvpp*x*_m3_lishield c0 c1 b m=,mcon/via/via2,li/m1/m2/m3,via3/via4,m4/m5,none,li/mcon/m1/via/m2/via2/m3,neighboring metal to VPP metal,none
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Varactor,xXXXXX xcnwvc c0 c1 b l w m,licon/mcon/via,diff/poly/li/m1/m2,via2,m3,none,poly/li/m1/m2,nwdiodemodel/m3*,none
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Inductor,xXXXXX xindXXXX t1 t2 body (note: no special RCX implementation for inductor required since black-box LVS will be used),via,m2/Cu,Nothing extracted within inductor.dg layer,,none,m2/via/Cu,Nothing extracted within inductor.dg layer,none
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Name Description Model Structure Modeled RX Actual CAD RX RX Discrepancy Modeled CX Actual CX CX Discrepancy
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Notes Contacts Sheets Contacts Sheets Sheet Sheet
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All Periphery FETs mXXXX d g s b w l m ad as pd ps nrd nrs none diff(min) licon/mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3 li-negligible
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20V NDEFETs NONISO xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3 li-negligible
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20V NDEFETs ISO xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li/sky130_fd_pr__model__parasitic__diode_ps2dn li/m1/m2-m3 li-negligible
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20V PDEFETs xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3/sky130_fd_pr__model__parasitic__diode_ps2dn__hv li-negligible
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Cell FETs NOT EXTRACTED FROM LAYOUT N/A N/A N/A N/A N/A N/A N/A N/A
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All Diodes dXXXX n1 n2 area pj licon diff licon/mcon/vias poly/li/m1/m2-m3 licon-negligible Junction li/m1/m2-m3 none
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RF ESD Diodes xesd_XXXX n1 n2 area pj licon/mcon/via li/m1/m2 via2 m3 none li/m1/m2 m3 none
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pnp_05v5 Parasitic PNP qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W0p68L0p68 m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
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Parasitic PNP (5X) qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W3p40L3p40 m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
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npn_05v0 Parasitic NPN qXXXX nc nb ne ns sky130_fd_pr__npn_05v5 m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
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res_generic_XXX Non-precision Resistors rXXXX a b l w m none sheet layer licon/mcon/vias none (no sheet resistance where sheet layer & res id layer intersect) none none junction/li/m1/m2-m3 parasitic capacitance to substrate (tool limitation)
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res_iso_pw Isolated Pwell Resistor xXXXX pwres r0 r1 b l w m licon/mcon pwell/li vias m1/m2-m3 none none junction/m1/m2-m3 li-negligible
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res_high_XXX Precision poly resistor xXXXXX hrpoly_X_X r0 r1 b l w m licon/mcon poly/li via m1/m2-m3 none poly-sub m1/m2-m3 li-negligible
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cap_mim_XXXX MIM Capacitor (2-terminal) xXXXX sky130_fd_pr__cap_mim_m3_2 c0 c1 w l m via2 m3 N/A poly/li/m1/m2 m2 (of the device) -negligible capm-m2 li/m1/m2-m3 routing layers underneath device
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cap_mim_XXXX MIM Capacitor (3-terminal) xXXXX sky130_fd_pr__model__cap_mim c0 c1 b w l m via2 m3 N/A poly/li/m1/m2 m2 (of the device) -negligible m2-sub/capm-m2 (1) Carea of M2-sub (non-overlap CAPM w/ 0.14um upsize) (2) M3 Cap by 1 snap grid width none
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cap_vpp_XXXX Vertical Parallel Plate Cap xXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b m No special RCX implementation for VPP required since black-box LVS will be used mcon/via li/m1/m2 none (black box LVS) none (black box LVS) none li/mcon//m1/via/m2 none (black box LVS) Parasitic capacitance to routing above
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cap_vpp_XXXX Vertical Parallel Plate Cap over MOSCAP xXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b m mcon/via li/m1/m2 none (black box LVS) none (black box LVS) none li/mcon//m1/via/m2 none (black box LVS) Parasitic capacitance to routing above
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cap_vpp_XXXX 4-terminal Vertical Parallel Plate Cap (M3 Shielded) xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m= licon/mcon/via poly/li/m1/m2 via3/via4 m3/m4/m5 none poly/licon/li/mcon/m1/via/m2/m3 m3-substrate (not m3-m2), neighboring metal to VPP metal none
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cap_vpp_XXXX 4-terminal Vertical Parallel Plate Cap (M5 Shielded) xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m= licon/mcon/via/via2/via3 poly/li/m1/m2/m3/m4 via4 m5 none poly/licon/li/mcon/m1/via/m2/m3/m4/m5 neighboring metal to VPP metal none
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cap_vpp_XXXX 3-terminal Vertical Parallel Plate Cap xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= mcon/via li/m1/m2 via2/via3/via4 m3/m4/m5 none li/mcon/m1/via/m2 neighboring metal to VPP metal Parasitic capacitance to routing above
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cap_vpp_XXXX 3-terminal Vertical Parallel Plate Cap xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= mcon/via/via2 li/m1/m2/m3 via3/via4 m4/m5 none li/mcon/m1/via/m2/via2/m3 neighboring metal to VPP metal none
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cap_var_XXXX Varactor xXXXXX sky130_fd_pr__cap_var_XXXX c0 c1 b l w m licon/mcon/via diff/poly/li/m1/m2 via2 m3 none poly/li/m1/m2 nwdiodemodel/m3* none
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Inductor xXXXXX xindXXXX t1 t2 body No special RCX implementation for inductor required since black-box LVS will be used via m2/Cu Nothing extracted within inductor.dg layer none m2/via/Cu Nothing extracted within inductor.dg layer none
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#!/usr/bin/env python3
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import csv
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import os
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import pprint
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import sys
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__dir__ = os.path.dirname(os.path.abspath(__file__))
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TSV_FILE = os.path.join(__dir__, "rcx-all.tsv")
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def main(arg):
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rows = []
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with open(TSV_FILE, newline='') as csvfile:
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reader = csv.reader(csvfile, delimiter='\t')
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for r in reader:
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rows.append(list(c.strip() for c in r))
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rowlen = max(len(r) for r in rows)
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for r in rows:
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while len(r) < rowlen:
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r.append('')
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clen = [0] * rowlen
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for i, _ in enumerate(clen):
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clen[i] = max(len(r[i]) for r in rows)
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for r in rows:
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for i, m in enumerate(clen):
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r[i] = r[i].ljust(m)
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rows.insert(1, ['-'*m for m in clen])
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for r in rows:
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print("|", " | ".join(r), "|")
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return 0
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if __name__ == "__main__":
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sys.exit(main(sys.argv))
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