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docs: Whitespace fixes.

This commit is contained in:
Tim 'mithro' Ansell 2020-09-10 16:51:10 -07:00
parent 6e8b54e3c9
commit b581da870a
1 changed files with 5 additions and 5 deletions
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10
docs/rules/rcx/rcx-all.csv
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@ -6,7 +6,7 @@ All Periphery FETs,mXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min),licon/
20V PDEFETs,xXXXX d g s b w l m ad as pd ps nrd nrs,none,diff(min)/licon,mcon/vias, diff(ext)/poly/li/m1/m2-m3,none,poly/licon/li,li/m1/m2-m3/dnwhvdiode_psub,li-negligible
Cell FETs,NOT EXTRACTED FROM LAYOUT,N/A,N/A,N/A,N/A,N/A,N/A,N/A,N/A
All Diodes,dXXXX n1 n2 area pj,licon,diff,licon/mcon/vias, poly/li/m1/m2-m3,licon-negligible,Junction,li/m1/m2-m3,none
RF ESD Diodes,xesd_XXXX n1 n2 area pj,licon/mcon/ via,li/m1/m2,via2,m3,none,li/m1/m2,m3,none
RF ESD Diodes,xesd_XXXX n1 n2 area pj,licon/mcon/via,li/m1/m2,via2,m3,none,li/m1/m2,m3,none
Parasitic PNP,qXXXX nc nb ne ns pnppar m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
Parasitic PNP (5X),qXXXX nc nb ne ns pnppar5x m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
Parasitic NPN,qXXXX nc nb ne ns npnpar m,licon/mcon,diff/li,mcon/vias,li/m1/m2-m3,li/mcon-neglible,na,li/m1/m2-m3,none
@ -17,9 +17,9 @@ MIM Capacitor (3-terminal),xXXXX xcmimc c0 c1 b w l m ,via2,m3,N/A,poly/li/m1/m2
Isolated Pwell Resistor,xXXXX pwres r0 r1 b l w m,licon/mcon,pwell/li,vias,m1/m2-m3,none,none,junction/m1/m2-m3,li-negligible
Vertical Parallel Plate Cap,xXXXX xcmvpp c0 c1 b m (note: no special RCX implementation for VPP required since black-box LVS will be used),mcon/via,li/m1/m2,none (black box LVS),none (black box LVS),none,li/mcon//m1/via/m2,none (black box LVS),Parasitic capacitance to routing above
Vertical Parallel Plate Cap over MOSCAP,xXXXX xcmvpp2_* c0 c1 b m ,mcon/via,li/m1/m2,none (black box LVS),none (black box LVS),none,li/mcon//m1/via/m2,none (black box LVS),Parasitic capacitance to routing above
4-terminal Vertical Parallel Plate Cap (M3 Shielded),xXXXXX xcmvpp*x*_m3shield c0 c1 b term4 m=,licon/mcon/ via,poly/li/m1/m2,via3/via4,m3/m4/m5,none,poly/licon/li/mcon/m1/via/m2/m3,"m3-substrate (not m3-m2), neighboring metal to VPP metal",none
4-terminal Vertical Parallel Plate Cap (M5 Shielded),xXXXXX xcmvpp*_*m5shield c0 c1 b term4 m=,licon/mcon/ via/via2/via3,poly/li/m1/m2/m3/m4,via4,m5,none,poly/licon/li/mcon/m1/via/m2/m3/m4/m5,neighboring metal to VPP metal,none
3-terminal Vertical Parallel Plate Cap,xXXXXX xcmvpp*x* c0 c1 b m=\nxXXXXX xcmvpp*x*_lishield c0 c1 b m=,mcon/ via,li/m1/m2,via2/via3/via4,m3/m4/m5,none,li/mcon/m1/via/m2,neighboring metal to VPP metal,Parasitic capacitance to routing above
3-terminal Vertical Parallel Plate Cap (for S8Q/S8P only),xXXXXX xcmvpp*x*_m3_lishield c0 c1 b m=,mcon/ via/via2,li/m1/m2/m3,via3/via4,m4/m5,none,li/mcon/m1/via/m2/via2/m3,neighboring metal to VPP metal,none
4-terminal Vertical Parallel Plate Cap (M3 Shielded),xXXXXX xcmvpp*x*_m3shield c0 c1 b term4 m=,licon/mcon/via,poly/li/m1/m2,via3/via4,m3/m4/m5,none,poly/licon/li/mcon/m1/via/m2/m3,"m3-substrate (not m3-m2), neighboring metal to VPP metal",none
4-terminal Vertical Parallel Plate Cap (M5 Shielded),xXXXXX xcmvpp*_*m5shield c0 c1 b term4 m=,licon/mcon/via/via2/via3,poly/li/m1/m2/m3/m4,via4,m5,none,poly/licon/li/mcon/m1/via/m2/m3/m4/m5,neighboring metal to VPP metal,none
3-terminal Vertical Parallel Plate Cap,xXXXXX xcmvpp*x* c0 c1 b m=\nxXXXXX xcmvpp*x*_lishield c0 c1 b m=,mcon/via,li/m1/m2,via2/via3/via4,m3/m4/m5,none,li/mcon/m1/via/m2,neighboring metal to VPP metal,Parasitic capacitance to routing above
3-terminal Vertical Parallel Plate Cap (for S8Q/S8P only),xXXXXX xcmvpp*x*_m3_lishield c0 c1 b m=,mcon/via/via2,li/m1/m2/m3,via3/via4,m4/m5,none,li/mcon/m1/via/m2/via2/m3,neighboring metal to VPP metal,none
Varactor,xXXXXX xcnwvc c0 c1 b l w m,licon/mcon/via,diff/poly/li/m1/m2,via2,m3,none,poly/li/m1/m2,nwdiodemodel/m3*,none
Inductor,xXXXXX xindXXXX t1 t2 body (note: no special RCX implementation for inductor required since black-box LVS will be used),via,m2/Cu,Nothing extracted within inductor.dg layer,,none,m2/via/Cu,Nothing extracted within inductor.dg layer,none

1 Description Model Structure Modeled RX Actual CAD RX RX Discrepancy Modeled CX Actual CX CX Discrepancy
6 20V PDEFETs xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3/dnwhvdiode_psub li-negligible
7 Cell FETs NOT EXTRACTED FROM LAYOUT N/A N/A N/A N/A N/A N/A N/A N/A
8 All Diodes dXXXX n1 n2 area pj licon diff licon/mcon/vias poly/li/m1/m2-m3 licon-negligible Junction li/m1/m2-m3 none
9 RF ESD Diodes xesd_XXXX n1 n2 area pj licon/mcon/ via licon/mcon/via li/m1/m2 via2 m3 none li/m1/m2 m3 none
10 Parasitic PNP qXXXX nc nb ne ns pnppar m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
11 Parasitic PNP (5X) qXXXX nc nb ne ns pnppar5x m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
12 Parasitic NPN qXXXX nc nb ne ns npnpar m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
17 Isolated Pwell Resistor xXXXX pwres r0 r1 b l w m licon/mcon pwell/li vias m1/m2-m3 none none junction/m1/m2-m3 li-negligible
18 Vertical Parallel Plate Cap xXXXX xcmvpp c0 c1 b m (note: no special RCX implementation for VPP required since black-box LVS will be used) mcon/via li/m1/m2 none (black box LVS) none (black box LVS) none li/mcon//m1/via/m2 none (black box LVS) Parasitic capacitance to routing above
19 Vertical Parallel Plate Cap over MOSCAP xXXXX xcmvpp2_* c0 c1 b m mcon/via li/m1/m2 none (black box LVS) none (black box LVS) none li/mcon//m1/via/m2 none (black box LVS) Parasitic capacitance to routing above
20 4-terminal Vertical Parallel Plate Cap (M3 Shielded) xXXXXX xcmvpp*x*_m3shield c0 c1 b term4 m= licon/mcon/ via licon/mcon/via poly/li/m1/m2 via3/via4 m3/m4/m5 none poly/licon/li/mcon/m1/via/m2/m3 m3-substrate (not m3-m2), neighboring metal to VPP metal none
21 4-terminal Vertical Parallel Plate Cap (M5 Shielded) xXXXXX xcmvpp*_*m5shield c0 c1 b term4 m= licon/mcon/ via/via2/via3 licon/mcon/via/via2/via3 poly/li/m1/m2/m3/m4 via4 m5 none poly/licon/li/mcon/m1/via/m2/m3/m4/m5 neighboring metal to VPP metal none
22 3-terminal Vertical Parallel Plate Cap xXXXXX xcmvpp*x* c0 c1 b m=\nxXXXXX xcmvpp*x*_lishield c0 c1 b m= mcon/ via mcon/via li/m1/m2 via2/via3/via4 m3/m4/m5 none li/mcon/m1/via/m2 neighboring metal to VPP metal Parasitic capacitance to routing above
23 3-terminal Vertical Parallel Plate Cap (for S8Q/S8P only) xXXXXX xcmvpp*x*_m3_lishield c0 c1 b m= mcon/ via/via2 mcon/via/via2 li/m1/m2/m3 via3/via4 m4/m5 none li/mcon/m1/via/m2/via2/m3 neighboring metal to VPP metal none
24 Varactor xXXXXX xcnwvc c0 c1 b l w m licon/mcon/via diff/poly/li/m1/m2 via2 m3 none poly/li/m1/m2 nwdiodemodel/m3* none
25 Inductor xXXXXX xindXXXX t1 t2 body (note: no special RCX implementation for inductor required since black-box LVS will be used) via m2/Cu Nothing extracted within inductor.dg layer none m2/via/Cu Nothing extracted within inductor.dg layer none