Cell readme generator updated, includes GDS2 layouts
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@ -10,10 +10,8 @@
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# SPDX-License-Identifier: Apache-2.0
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# SPDX-License-Identifier: Apache-2.0
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''' This is a prototype of cell documentation generation script.
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''' This is a prototype of cell documentation generation script.
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WORK IN PROGRESS
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'''
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'''
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import csv
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import csv
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import json
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import json
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import os
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import os
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@ -24,40 +22,105 @@ import glob
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import subprocess
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import subprocess
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import textwrap
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import textwrap
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readme_template ="""\
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{header}
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{headerUL}
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**{description}**
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*This is a stub of cell description file*
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- **Cell name**: {name}
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- **Type**: {deftype}
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- **Verilog name**: {verilog_name}
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- **Library**: {library}
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- **Inputs**: {inputs}
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- **Outputs**: {outputs}
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Symbols
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-------
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.. list-table::
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* - .. figure:: {symbol1}
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-
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- .. figure:: {symbol2}
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Schematic
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---------
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.. figure:: {schematic}
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:align: center
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GDSII Layouts
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-------------
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"""
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figure_template ="""
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.. figure:: {fig}
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:align: center
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:width: 50%
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{name}
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"""
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def write_readme(cellpath, define_data):
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def write_readme(cellpath, define_data):
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''' Generates README for a given cell.
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''' Generates README for a given cell.
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Args:
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cellpath - path to a cell [str of pathlib.Path]
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define_data - cell data from json [dic]
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'''
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'''
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netlist_json = os.path.join(cellpath, define_data['file_prefix']+'.json')
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netlist_json = os.path.join(cellpath, define_data['file_prefix']+'.json')
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assert os.path.exists(netlist_json), netlist_json
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assert os.path.exists(netlist_json), netlist_json
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outpath = os.path.join(cellpath, 'README.rst')
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outpath = os.path.join(cellpath, 'README.rst')
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header = define_data['name'] + ' cell description'
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headline = '-' * len(header)
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prefix = define_data['file_prefix']
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prefix = define_data['file_prefix']
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header = prefix
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sym1 = prefix + '.symbol.svg'
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symbol1 = prefix + '.symbol.svg'
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sym2 = prefix + '.pp.symbol.svg'
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symbol2 = prefix + '.pp.symbol.svg'
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sche = prefix + '.schematic.svg'
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schematic = prefix + '.schematic.svg'
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inputs = []
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outputs = []
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for p in define_data['ports']:
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try:
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if p[0]=='signal' and p[2]=='input':
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inputs.append(p[1])
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if p[0]=='signal' and p[2]=='output':
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outputs.append(p[1])
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except:
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pass
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gdssvg = []
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svglist = list(pathlib.Path(cellpath).glob('*.svg'))
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for s in svglist:
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gdsfile = pathlib.Path(os.path.join(cellpath, s.stem +'.gds'))
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if gdsfile.is_file():
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gdssvg.append(s)
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with open(outpath, 'w') as f:
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with open(outpath, 'w') as f:
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f.write (f'{header}\n')
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f.write (readme_template.format (
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f.write (f'{headline}\n')
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header = header,
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f.write ('\nThis is a stub of cell descrition file.\n\n')
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headerUL = '=' * len(header),
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description = define_data['description'].rstrip('.'),
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f.write (f" * Name: {define_data['name']}\n")
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name = ':cell:`' + prefix +'`',
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f.write (f" * Type: {define_data['type']}\n")
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deftype = define_data['type'],
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f.write (f" * Verilog name: {define_data['verilog_name']}\n")
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verilog_name = define_data['verilog_name'],
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desc = textwrap.indent(define_data['description'], ' ').lstrip(),
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library = define_data['library'],
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f.write (f" * Description: {desc}\n")
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inputs = f'{len(inputs)} (' + ', '.join(inputs) + ')',
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outputs = f'{len(outputs)} (' + ', '.join(outputs) + ')',
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f.write ('\nSome sample images:\n')
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symbol1 = symbol1,
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symbol2 = symbol2,
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f.write (f'\n.. image:: {sym1}\n :align: center\n :alt: Symbol\n')
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schematic = schematic,
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f.write (f'\n.. image:: {sym2}\n :align: center\n :alt: SymbolPP\n')
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))
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f.write (f'\n.. image:: {sche}\n :align: center\n :alt: Schematic\n')
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for gs in sorted(gdssvg):
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f.write (figure_template.format (
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fig = gs.name,
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name = gs.stem
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))
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def process(cellpath):
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def process(cellpath):
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''' Processes cell indicated by path.
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''' Processes cell indicated by path.
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