diff --git a/scripts/python-skywater-pdk/skywater_pdk/cell-readme-generate.py b/scripts/python-skywater-pdk/skywater_pdk/cell_readme_generate.py similarity index 58% rename from scripts/python-skywater-pdk/skywater_pdk/cell-readme-generate.py rename to scripts/python-skywater-pdk/skywater_pdk/cell_readme_generate.py index b4d2c8b..82a30c3 100755 --- a/scripts/python-skywater-pdk/skywater_pdk/cell-readme-generate.py +++ b/scripts/python-skywater-pdk/skywater_pdk/cell_readme_generate.py @@ -10,10 +10,8 @@ # SPDX-License-Identifier: Apache-2.0 ''' This is a prototype of cell documentation generation script. - WORK IN PROGRESS ''' - import csv import json import os @@ -24,40 +22,105 @@ import glob import subprocess import textwrap + +readme_template ="""\ +{header} +{headerUL} + +**{description}** + +*This is a stub of cell description file* + +- **Cell name**: {name} +- **Type**: {deftype} +- **Verilog name**: {verilog_name} +- **Library**: {library} +- **Inputs**: {inputs} +- **Outputs**: {outputs} + +Symbols +------- + +.. list-table:: + + * - .. figure:: {symbol1} + - + - .. figure:: {symbol2} + +Schematic +--------- + +.. figure:: {schematic} + :align: center + +GDSII Layouts +------------- + +""" + +figure_template =""" + +.. figure:: {fig} + :align: center + :width: 50% + + {name} +""" + def write_readme(cellpath, define_data): ''' Generates README for a given cell. + + Args: + cellpath - path to a cell [str of pathlib.Path] + define_data - cell data from json [dic] + ''' netlist_json = os.path.join(cellpath, define_data['file_prefix']+'.json') assert os.path.exists(netlist_json), netlist_json outpath = os.path.join(cellpath, 'README.rst') - header = define_data['name'] + ' cell description' - headline = '-' * len(header) - prefix = define_data['file_prefix'] - - sym1 = prefix + '.symbol.svg' - sym2 = prefix + '.pp.symbol.svg' - sche = prefix + '.schematic.svg' + header = prefix + symbol1 = prefix + '.symbol.svg' + symbol2 = prefix + '.pp.symbol.svg' + schematic = prefix + '.schematic.svg' + inputs = [] + outputs = [] + for p in define_data['ports']: + try: + if p[0]=='signal' and p[2]=='input': + inputs.append(p[1]) + if p[0]=='signal' and p[2]=='output': + outputs.append(p[1]) + except: + pass + gdssvg = [] + svglist = list(pathlib.Path(cellpath).glob('*.svg')) + for s in svglist: + gdsfile = pathlib.Path(os.path.join(cellpath, s.stem +'.gds')) + if gdsfile.is_file(): + gdssvg.append(s) - with open(outpath, 'w') as f: - f.write (f'{header}\n') - f.write (f'{headline}\n') - f.write ('\nThis is a stub of cell descrition file.\n\n') - - f.write (f" * Name: {define_data['name']}\n") - f.write (f" * Type: {define_data['type']}\n") - f.write (f" * Verilog name: {define_data['verilog_name']}\n") - desc = textwrap.indent(define_data['description'], ' ').lstrip(), - f.write (f" * Description: {desc}\n") - - f.write ('\nSome sample images:\n') - - f.write (f'\n.. image:: {sym1}\n :align: center\n :alt: Symbol\n') - f.write (f'\n.. image:: {sym2}\n :align: center\n :alt: SymbolPP\n') - f.write (f'\n.. image:: {sche}\n :align: center\n :alt: Schematic\n') - + f.write (readme_template.format ( + header = header, + headerUL = '=' * len(header), + description = define_data['description'].rstrip('.'), + name = ':cell:`' + prefix +'`', + deftype = define_data['type'], + verilog_name = define_data['verilog_name'], + library = define_data['library'], + inputs = f'{len(inputs)} (' + ', '.join(inputs) + ')', + outputs = f'{len(outputs)} (' + ', '.join(outputs) + ')', + symbol1 = symbol1, + symbol2 = symbol2, + schematic = schematic, + )) + for gs in sorted(gdssvg): + f.write (figure_template.format ( + fig = gs.name, + name = gs.stem + )) def process(cellpath): ''' Processes cell indicated by path.