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docs: Adding layer information from section C documentation. 

Signed-off-by: Tim 'mithro' Ansell <me@mith.ro>
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Tim 'mithro' Ansell 2020-07-23 13:58:43 -07:00
parent 8c11d93428
commit 8b5a8cede1
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SkyWater GDS Layers Information
===============================
The :download:`gds_layers.csv file <./gds_layers.csv>` provides a raw list of the
layers used in the process with name, description and the GDS layer and data type.
.. csv-table:: Table - GDS Layers
:file: gds_layers.csv
:header-rows: 1
:widths: 10, 15, 10, 75

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Device, LVS and other CAD definitions
=====================================
Layers Definitions
------------------
.. csv-table:: Table C3: Device, LVS and other CAD definitions
:file: layers/table-c3-device-lvs-other.csv
:header-rows: 1
Auxiliary Layers
----------------
.. csv-table:: Table C4a: Purpose layer description in LSW window and Auxiliary Layers
:file: layers/table-c4a-layer-description.csv
:header-rows: 1
.. csv-table:: Table C4b: Purpose layer description in LSW window and Auxiliary Layers
:file: layers/table-c4b-layer-description.csv
:header-rows: 1
GDS Layers Information
----------------------
The :download:`gds_layers.csv file <./gds_layers.csv>` provides a raw list of the
layers used in the process with name, description and the GDS layer and data type.
.. csv-table:: Table - GDS Layers
:file: gds_layers.csv
:header-rows: 1
:widths: 10, 15, 10, 75

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Name,Defining algorithm,,,Used in …
AR_met2_A,Net Area Ratio of met2 not connected to via and of via2 >=0.05 [Equation: (AREA(via2))/(2 * AREA(met2NotConnVia) + PERIMETER(met2NotConnVia) * 0.35)],,,Rules
AR_met2_B,"Net Area Ratio of met2GroundOrFloat, via, and via2 <=0.032 [Equation: (AREA(via2))/(2 * AREA(met2GroundOrFloatVia) + PERIMETER(met2GroundOrFloatVia) * 0.35)]",,,Rules
bondPad,pad:dg OUTSIDE areaid:ft,,,Rules
bottom_plate,(capm:dg AND met2:dg) sized by capm.3; Exclude all capm sharing same metal2 plate,,,Rules
Capacitor,Capm enclosing at least one via2,,,Rules
Chip_extent,Holes (areaid:sl ) OR areaid.sl,,,Rules
Diecut_pmm,areaid.dt NOT (cfom.wp OR cp1m.wp OR cmm1.wp OR cmm2.wp),,,Rules
drain_diffusion,(diff NOT poly in nwell or pwell) not abutting tap in the same well or abutting tap in the opposite well,,,Rules
dummy_capacitor,Capm not overlapping via2,,,Rules
dummy_poly,"poly overlapping text ""dummy_poly"" (written using text.dg)",,,Rules
ESD_nwell_tap,"n+ tap coincident with nwell such that n+ tap and nwell are completely surrounded by and abutting n+ diff on all edges, within areaid:ed ",,,Rules
fomDmy_keepout_1, (diff.dg OR tap.dg OR poly.dg OR pwell resistor OR pad OR cfom.dg OR cfom.mk OR PhotoArray OR cp1m.mk),,,Rules
floating_met*,met*.dg not connected to diffusion or tap through met(*+1) or met(*-1) and their respecitve vias and contacts,,,Rules
fom_waffles,"fom.mk with dimensions (um x um): 0.5 x 0.5, 1.5 x 1.5, 2.5 x 2.5 and 4.08 x 4.08",,,Rules
gated_npn,cell name: s8rf_npn_1x1_2p0_HV,,,Rules
huge_metX,Metal X geometry wider and longer than 3.000um,,,Rules
hugePad,pad.mk with width > 100um,,,Rules
iso_pwell,(NOT nwell) AND dnwell,,,Rules
isolated_tap,tap that does not abut diff,,,Rules
laser_target,cell *lazX_* and *lazY_* OUTSIDE areaid:ft,,,Rules
LVnwell,nwell NOT hvi,,,Rules
LVTN_Gate,Gate overlapping lvtn,,,Rules
met2GroundOrFloat,met2 connected to ptap or met2 not connected to difftap\n,,,Rules
met2GroundOrFloatVia,met2GroundOrFloat interacting with via2 >2,,,Rules
N+_diff,Diff NOT Nwell,,,Rules
N+_tap,Tap AND Nwell,,,Rules
nsdmHoles,Hole( nsdm ),,,Rules
NSM_keepout,nsm.dg OR nsm.mk,,,Rules
nwell_all,nwell OR extension of cnwm beyond nwell edge straddling de_nFet_source by cnwm.3f (45 degree edges are retained for the NVHV device nwell); Rule cnwm.3f applies only to GSMC flows,,,Rules
P+_diff,Diff AND Nwell,,,Rules
P+_tap,Tap NOT Nwell,,,Rules
Pattern_density,(diff_tap area) / PD window (as specified in the rule section),,,Rules
photoDiode,deep nwell overlapping areaid.po. Die+frame utility will use the mask data of dnwell in the implementation of this definition,,,Rules
poly_licon1,Any licon1 that does not overlap ((diff or tap) NOT poly),,,Rules
poly_waffles,"p1m.mk with dimensions (um x um): 0.48 x 0.48, 0.54 x 0.54 and 0.72 x 0.72",,,Rules
prec_resistor,rpm AND (poly overlapping poly.rs) AND psdm,,,Rules
prec_resistor_terminal,prec_resistor AND li,,,Rules
psdmHoles,Hole( psdm ),,,Rules
pwell,NOT nwell (default substrate area),,,Rules
pwres_terminal,P+tap abutting pwell.rs,,,Rules
pnp_emitter,diff AND pnp.dg AND psdm,,,Rules
routing_terminal,metX.pin sized inside of metX.drawing by 1/2 * metalX min width; Similar defintion applies to Li1 layer,,,Rules
scribe_line,areaid:ft NOT areaid:dt,,,Rules
slotted_licon,licon1.dg of size 0.19um x 2.0um,,,Rules
slotted_licon_edge1,2.0um edge of the slotted_licon,,,Rules
source_diffusion,(diff NOT poly in nwell or pwell) abutting tap in same well,,,Rules
tap_licon,Tap AND Licon1,,,Rules
tap_notPoly,tap NOT poly,,,Rules
top_indmMetal,met3 for S8D*,,,Rules
top_metal,met3.dg OR mm3.mk (for S8T*/SP8TEE-5R); met3.dg OR indm.mk (for S8D*); met4.dg OR mm4.mk (for SP8Q/S8Q*); met5.dg OR mm5.mk (for SP8P*/S8P*),,,Rules
top_padVia,Via2 for S8D*,,,Rules
top_plate,capm:dg,,,Rules
Var_channel,poly AND tap AND (nwell NOT hvi) NOT areaid.ce,,,Rules
VaracTap,Tap overlapping Var_channel,,,Rules
vpp_with_noLi,"vpp with cell names: s8rf2_xcmvpp3, s8rf2_xcmvpp4, s8rf2_xcmvpp5, s8rf2_xcmvpp4p4x4p6_m1m2, s8rf2_xcmvpp11p5x11p7_m1m2, s8rf2_xcmvpp11p5x11p7_m1m4, s8rf2_xcmvpp11p5x11p7_m1m4m5shield",,,Rules
vpp_with_Met3Shield,"vpp with cell names: s8rf_xcmvpp1p8x1p8_m3shield, s8rf_xcmvpp4p4x4p6_m3shield, s8rf_xcmvpp8p6x7p9_m3shield, s8rf_xcmvpp11p5x11p7_m3shield",,,Rules
vpp_with_LiShield,vpp with cell names: s8rf*_li*shield,,,Rules
vpp_over_MOSCAP,"vpp with cell names: s8rf_xcmvpp2 when over nhvnative W/L=10x4, s8rf_xcmvpp2_nwell when over phv/pshort/phighvt/plowvt W/L=5x4",,,Rules
vpp_with_Met5PolyShield,"vpp with cell names: s8rf2_xcmvpp11p5x11p7_polym5shield, s8rf2_xcmvpp11p5x11p7_polym4shield, s8rf2_xcmvpp2x4_2xnhvnative10x4, s8rf2_xcmvpp6p8x6p1_polym4shield, s8rf2_xcmvpp11p5x11p7_polym50p4shield, s8rf2_xcmvpp_hd5_*",,,Rules
vpp_with_Met5,"vpp with cell names: s8rf2_xcmvpp11p5x11p7_m5shield, s8rf2_xcmvpp11p5x11p7_polym5shield, s8rf2_xcmvpp11p5x11p7_lim5shield, s8rf2_xcmvpp8p6x7p9_m3_lim5shield, s8rf2_xcmvpp2x4_2xnhvnative10x4, s8rf2_xcmvpp11p5x11p7_m4shield, s8rf2_xcmvpp11p5x11p7_polym4shield, s8rf2_xcmvpp6p8x6p1_polym4shield, s8rf2_xcmvpp6p8x6p1_lim4shield, s8rf2_xcmvpp11p5x11p7_m3_lim5shield, s8rf2_xcmvpp4p4x4p6_m3_lim5shield, s8rf2_xcmvpp11p5x11p7_m1m4m5shield, s8rf2_xcmvpp11p5x11p7_m1m4\ns8rf2_xcmvpp11p5x11p7_polym50p4shield, s8rf2_xcmvpp_hd5_*",,,Rules
cp1m_HV,cp1m AND Hvi,,,Rules (HV)
de_nFet_drain,((isolated tap) AND areaid.en) overlapping nwell,,,Rules (HV)
de_nFET_gate,deFET_gate overlapping (diff NOT dnwell),,,Rules (HV)
de_nFet_source,(diff AND areaid.en) overlapping de_nFET_gate,,,Rules (HV)
de_pFet_drain,((isolated tap) AND areaid.en) not overlapping nwell,,,Rules (HV)
de_pFET_gate,deFET_gate overlapping (diff AND dnwell),,,Rules (HV)
de_pFet_source,(diff AND areaid.en) overlapping de_pFET_gate,,,Rules (HV)
deFET_gate,"(poly AND areaid.en) not overlapping pwm ; For CAD flows that do not have pwm layer, it is (poly AND areaid.en)",,,Rules (HV)
Hdiff,Diffusion AND Hvi,,,Rules (HV)
Hgate,Hpoly AND diff,,,Rules (HV)
Hnwell,Nwell AND Hvi,,,Rules (HV)
Hpoly,Poly AND Hvi,,,Rules (HV)
Htap,Tap AND Hvi,,,Rules (HV)
hv_source/drain,= (diff andNot poly) that overlaps diff.hv,,,Rules (HV)
hvFET_gate,= FET_gate butting hv_source/drain,,,Rules (HV)
hvPoly,= poly electrically connected to hv_source/drain,,,Rules (HV)
HV_nwell,(nwell AND hvi) OR (nwell overlapping areaid.hl),,,Rules (HV)
stack_hv_lv_diff,(diff And Hvi NOT nwell) abutting (diff NOT nwell),,,Rules (HV)
SHVdiff,Diff And shvi,,,Rules (SHV)
SHVGate,SHVPoly AND diff,,,Rules (SHV)
SHVPoly,Poly OVERLAP shvi:dg,,,Rules (SHV)
SHVSourceDrain,Diff And shvi NOT poly NOT diff:rs,,,Rules (SHV)
VHVdiff,Diff And vhvi,,,Rules (VHV)
VHVGate,VHVPoly AND diff,,,Rules (VHV)
VHVPoly,Poly OVERLAP vhvi:dg,,,Rules (VHV)
VHVSourceDrain,(Diff AND tap) And vhvi NOT poly NOT diff:rs,,,Rules (VHV)
background,"Area where waffling grid is defined, sized to avoid waffle shift between runs",,,Waffles
die,Holes (areaid:sl ),,,Waffles
frame,( areaid.ft SIZE by -(max of s.2e/h)) NOT (OR areaid.dt SEALIDandHole),,,Waffles
inductor_metal,(inductor:dg AND (met1 OR met2 OR met3)) size by 10 um [For all flows except S8PIR-10R]\ninductor.dg [for the S8PIR-10R flow],,,Waffles
mm*_slot,mm* slots are defined as empty holes in metal that are located in (areaid.cr OR areaid.cd),,,Waffles
nwellDnwellHoles,(inner HOLES of nwellAndDnwell). Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition,,,Waffles
photoArray,(OR nwellAndDnwell nwellDnwellHoles) enclosing photoDiode. Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition,,,Waffles
gate,poly AND diff,,,"pfet, nfet (LVS)"
nfet,Gate NOT nwell,,,"pfet, nfet (LVS)"
pfet,Gate AND nwell,,,"pfet, nfet (LVS)"
nDiode,Ndiff AND DiodeID,,,Diodes (LVS)
Pdiff,diff AND nwell,,,Diodes (LVS)
pDiode,Pdiff AND DiodeID,,,Diodes (LVS)
diff_hole,Hole( diff ),,,ESD (LVS)
diff_tap_nwell,tap_nwell INSIDE diff_hole,,,ESD (LVS)
esd_diff_tap_nwell,ESDID AND diff_tap_nwell,,,ESD (LVS)
Ndiff,diff NOT nwell,,,ESD (LVS)
tap_nwell,tap INSIDE nwell,,,ESD (LVS)
ESD_diffusion,A+B31ny diffusion or ESD_nwell_tap connected directly or through a resistor to a Pad or to Vss/Vcc that is covered by areaid.ed and located within a double tap guardrings.,,,Latch up rules
ESD_cascode_diffusion,Diffusion covered by areaid.ed between two minimum spaced poly gates and located within a pair of double tap guardrings. (There should be no licons on the diffusion.),,,Latch up rules
ESD_diode,Any nwell (other than ESD_nwell_tap ) covered by areaid.ed and areaid.de that does not contain poly,,,Latch up rules
ESD_FET,(any Pdiff covered by areaid:ed within a double tap guardrings) Or\nESD_NFET,,,Latch up rules
ESD_NFET,(any Ndiff covered by areaid:ed abutting ESD_nwell_tap) Or (any Ndiff covered by areaid:ed abutting gate within 3.5um of ESD_nwell_tap) Or (any Ndiff abutting ESD_nwell_tap within areaid.ed) a double tap guardrings,,,Latch up rules
I/O_or_Output_Pmos,ESD P+ diffusion overlapping poly and overlapping ESD source/drain diffusion connected to I/O or output net,,,Latch up rules
I/O_Pmos_w/series_R,ESD PMOS connected to I/O or output net through series resistors,,,Latch up rules
met_ESD_resistor,Metal resistor inside areaid:ed,,,Latch up rules
Non_Vcc_nwell,Any nwell connected to any bias other than power supply,,,Latch up rules
Nwell_area,Is determined using the following steps:\n(a) Grow pdiff by 1.5 mm\n(b) Merge\n(c) And Nwell:dg,,,Latch up rules
Pwell_area,Is determined using the following steps:\n(a) Grow ndiff by 1.5 mm\n(b) Merge\n(c) NOT Nwell:dg,,,Latch up rules
Series_transistors,Merged diffusion determined by Nwell_area and Pwell_area,,,Latch up rules
fuse:dg,"met2:fe for S8D*/S8TM*, met3.fe for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*, met4.fe for S8P*/SP8P*",,,Fuse rules
fuse_contact,(fuse_metal overlapping fuse:dg) NOT fuse:dg,,,Fuse rules
fuse_metal,"met3 for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*; met2 for S8D*/S8TM*, met4 for S8P*/SP8P*",,,Fuse rules
fuse_shield,"Metal line (same metal level as fuse) between fuse and periphery, not overlapping contacts or vias, with specified dimensions",,,Fuse rules
non-isolated fuse edge,Long edge of the fuse spaced to Met2/Met3/Met4 less than a specified amount,,,Fuse rules
single_fuses,Fuses without neighboring fuses within specified distance,,,Fuse rules
1 Name Defining algorithm Used in …
2 AR_met2_A Net Area Ratio of met2 not connected to via and of via2 >=0.05 [Equation: (AREA(via2))/(2 * AREA(met2NotConnVia) + PERIMETER(met2NotConnVia) * 0.35)] Rules
3 AR_met2_B Net Area Ratio of met2GroundOrFloat, via, and via2 <=0.032 [Equation: (AREA(via2))/(2 * AREA(met2GroundOrFloatVia) + PERIMETER(met2GroundOrFloatVia) * 0.35)] Rules
4 bondPad pad:dg OUTSIDE areaid:ft Rules
5 bottom_plate (capm:dg AND met2:dg) sized by capm.3; Exclude all capm sharing same metal2 plate Rules
6 Capacitor Capm enclosing at least one via2 Rules
7 Chip_extent Holes (areaid:sl ) OR areaid.sl Rules
8 Diecut_pmm areaid.dt NOT (cfom.wp OR cp1m.wp OR cmm1.wp OR cmm2.wp) Rules
9 drain_diffusion (diff NOT poly in nwell or pwell) not abutting tap in the same well or abutting tap in the opposite well Rules
10 dummy_capacitor Capm not overlapping via2 Rules
11 dummy_poly poly overlapping text "dummy_poly" (written using text.dg) Rules
12 ESD_nwell_tap n+ tap coincident with nwell such that n+ tap and nwell are completely surrounded by and abutting n+ diff on all edges, within areaid:ed Rules
13 fomDmy_keepout_1 (diff.dg OR tap.dg OR poly.dg OR pwell resistor OR pad OR cfom.dg OR cfom.mk OR PhotoArray OR cp1m.mk) Rules
14 floating_met* met*.dg not connected to diffusion or tap through met(*+1) or met(*-1) and their respecitve vias and contacts Rules
15 fom_waffles fom.mk with dimensions (um x um): 0.5 x 0.5, 1.5 x 1.5, 2.5 x 2.5 and 4.08 x 4.08 Rules
16 gated_npn cell name: s8rf_npn_1x1_2p0_HV Rules
17 huge_metX Metal X geometry wider and longer than 3.000um Rules
18 hugePad pad.mk with width > 100um Rules
19 iso_pwell (NOT nwell) AND dnwell Rules
20 isolated_tap tap that does not abut diff Rules
21 laser_target cell *lazX_* and *lazY_* OUTSIDE areaid:ft Rules
22 LVnwell nwell NOT hvi Rules
23 LVTN_Gate Gate overlapping lvtn Rules
24 met2GroundOrFloat met2 connected to ptap or met2 not connected to difftap\n Rules
25 met2GroundOrFloatVia met2GroundOrFloat interacting with via2 >2 Rules
26 N+_diff Diff NOT Nwell Rules
27 N+_tap Tap AND Nwell Rules
28 nsdmHoles Hole( nsdm ) Rules
29 NSM_keepout nsm.dg OR nsm.mk Rules
30 nwell_all nwell OR extension of cnwm beyond nwell edge straddling de_nFet_source by cnwm.3f (45 degree edges are retained for the NVHV device nwell); Rule cnwm.3f applies only to GSMC flows Rules
31 P+_diff Diff AND Nwell Rules
32 P+_tap Tap NOT Nwell Rules
33 Pattern_density (diff_tap area) / PD window (as specified in the rule section) Rules
34 photoDiode deep nwell overlapping areaid.po. Die+frame utility will use the mask data of dnwell in the implementation of this definition Rules
35 poly_licon1 Any licon1 that does not overlap ((diff or tap) NOT poly) Rules
36 poly_waffles p1m.mk with dimensions (um x um): 0.48 x 0.48, 0.54 x 0.54 and 0.72 x 0.72 Rules
37 prec_resistor rpm AND (poly overlapping poly.rs) AND psdm Rules
38 prec_resistor_terminal prec_resistor AND li Rules
39 psdmHoles Hole( psdm ) Rules
40 pwell NOT nwell (default substrate area) Rules
41 pwres_terminal P+tap abutting pwell.rs Rules
42 pnp_emitter diff AND pnp.dg AND psdm Rules
43 routing_terminal metX.pin sized inside of metX.drawing by 1/2 * metalX min width; Similar defintion applies to Li1 layer Rules
44 scribe_line areaid:ft NOT areaid:dt Rules
45 slotted_licon licon1.dg of size 0.19um x 2.0um Rules
46 slotted_licon_edge1 2.0um edge of the slotted_licon Rules
47 source_diffusion (diff NOT poly in nwell or pwell) abutting tap in same well Rules
48 tap_licon Tap AND Licon1 Rules
49 tap_notPoly tap NOT poly Rules
50 top_indmMetal met3 for S8D* Rules
51 top_metal met3.dg OR mm3.mk (for S8T*/SP8TEE-5R); met3.dg OR indm.mk (for S8D*); met4.dg OR mm4.mk (for SP8Q/S8Q*); met5.dg OR mm5.mk (for SP8P*/S8P*) Rules
52 top_padVia Via2 for S8D* Rules
53 top_plate capm:dg Rules
54 Var_channel poly AND tap AND (nwell NOT hvi) NOT areaid.ce Rules
55 VaracTap Tap overlapping Var_channel Rules
56 vpp_with_noLi vpp with cell names: s8rf2_xcmvpp3, s8rf2_xcmvpp4, s8rf2_xcmvpp5, s8rf2_xcmvpp4p4x4p6_m1m2, s8rf2_xcmvpp11p5x11p7_m1m2, s8rf2_xcmvpp11p5x11p7_m1m4, s8rf2_xcmvpp11p5x11p7_m1m4m5shield Rules
57 vpp_with_Met3Shield vpp with cell names: s8rf_xcmvpp1p8x1p8_m3shield, s8rf_xcmvpp4p4x4p6_m3shield, s8rf_xcmvpp8p6x7p9_m3shield, s8rf_xcmvpp11p5x11p7_m3shield Rules
58 vpp_with_LiShield vpp with cell names: s8rf*_li*shield Rules
59 vpp_over_MOSCAP vpp with cell names: s8rf_xcmvpp2 when over nhvnative W/L=10x4, s8rf_xcmvpp2_nwell when over phv/pshort/phighvt/plowvt W/L=5x4 Rules
60 vpp_with_Met5PolyShield vpp with cell names: s8rf2_xcmvpp11p5x11p7_polym5shield, s8rf2_xcmvpp11p5x11p7_polym4shield, s8rf2_xcmvpp2x4_2xnhvnative10x4, s8rf2_xcmvpp6p8x6p1_polym4shield, s8rf2_xcmvpp11p5x11p7_polym50p4shield, s8rf2_xcmvpp_hd5_* Rules
61 vpp_with_Met5 vpp with cell names: s8rf2_xcmvpp11p5x11p7_m5shield, s8rf2_xcmvpp11p5x11p7_polym5shield, s8rf2_xcmvpp11p5x11p7_lim5shield, s8rf2_xcmvpp8p6x7p9_m3_lim5shield, s8rf2_xcmvpp2x4_2xnhvnative10x4, s8rf2_xcmvpp11p5x11p7_m4shield, s8rf2_xcmvpp11p5x11p7_polym4shield, s8rf2_xcmvpp6p8x6p1_polym4shield, s8rf2_xcmvpp6p8x6p1_lim4shield, s8rf2_xcmvpp11p5x11p7_m3_lim5shield, s8rf2_xcmvpp4p4x4p6_m3_lim5shield, s8rf2_xcmvpp11p5x11p7_m1m4m5shield, s8rf2_xcmvpp11p5x11p7_m1m4\ns8rf2_xcmvpp11p5x11p7_polym50p4shield, s8rf2_xcmvpp_hd5_* Rules
62 cp1m_HV cp1m AND Hvi Rules (HV)
63 de_nFet_drain ((isolated tap) AND areaid.en) overlapping nwell Rules (HV)
64 de_nFET_gate deFET_gate overlapping (diff NOT dnwell) Rules (HV)
65 de_nFet_source (diff AND areaid.en) overlapping de_nFET_gate Rules (HV)
66 de_pFet_drain ((isolated tap) AND areaid.en) not overlapping nwell Rules (HV)
67 de_pFET_gate deFET_gate overlapping (diff AND dnwell) Rules (HV)
68 de_pFet_source (diff AND areaid.en) overlapping de_pFET_gate Rules (HV)
69 deFET_gate (poly AND areaid.en) not overlapping pwm ; For CAD flows that do not have pwm layer, it is (poly AND areaid.en) Rules (HV)
70 Hdiff Diffusion AND Hvi Rules (HV)
71 Hgate Hpoly AND diff Rules (HV)
72 Hnwell Nwell AND Hvi Rules (HV)
73 Hpoly Poly AND Hvi Rules (HV)
74 Htap Tap AND Hvi Rules (HV)
75 hv_source/drain = (diff andNot poly) that overlaps diff.hv Rules (HV)
76 hvFET_gate = FET_gate butting hv_source/drain Rules (HV)
77 hvPoly = poly electrically connected to hv_source/drain Rules (HV)
78 HV_nwell (nwell AND hvi) OR (nwell overlapping areaid.hl) Rules (HV)
79 stack_hv_lv_diff (diff And Hvi NOT nwell) abutting (diff NOT nwell) Rules (HV)
80 SHVdiff Diff And shvi Rules (SHV)
81 SHVGate SHVPoly AND diff Rules (SHV)
82 SHVPoly Poly OVERLAP shvi:dg Rules (SHV)
83 SHVSourceDrain Diff And shvi NOT poly NOT diff:rs Rules (SHV)
84 VHVdiff Diff And vhvi Rules (VHV)
85 VHVGate VHVPoly AND diff Rules (VHV)
86 VHVPoly Poly OVERLAP vhvi:dg Rules (VHV)
87 VHVSourceDrain (Diff AND tap) And vhvi NOT poly NOT diff:rs Rules (VHV)
88 background Area where waffling grid is defined, sized to avoid waffle shift between runs Waffles
89 die Holes (areaid:sl ) Waffles
90 frame ( areaid.ft SIZE by -(max of s.2e/h)) NOT (OR areaid.dt SEALIDandHole) Waffles
91 inductor_metal (inductor:dg AND (met1 OR met2 OR met3)) size by 10 um [For all flows except S8PIR-10R]\ninductor.dg [for the S8PIR-10R flow] Waffles
92 mm*_slot mm* slots are defined as empty holes in metal that are located in (areaid.cr OR areaid.cd) Waffles
93 nwellDnwellHoles (inner HOLES of nwellAndDnwell). Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition Waffles
94 photoArray (OR nwellAndDnwell nwellDnwellHoles) enclosing photoDiode. Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition Waffles
95 gate poly AND diff pfet, nfet (LVS)
96 nfet Gate NOT nwell pfet, nfet (LVS)
97 pfet Gate AND nwell pfet, nfet (LVS)
98 nDiode Ndiff AND DiodeID Diodes (LVS)
99 Pdiff diff AND nwell Diodes (LVS)
100 pDiode Pdiff AND DiodeID Diodes (LVS)
101 diff_hole Hole( diff ) ESD (LVS)
102 diff_tap_nwell tap_nwell INSIDE diff_hole ESD (LVS)
103 esd_diff_tap_nwell ESDID AND diff_tap_nwell ESD (LVS)
104 Ndiff diff NOT nwell ESD (LVS)
105 tap_nwell tap INSIDE nwell ESD (LVS)
106 ESD_diffusion A+B31ny diffusion or ESD_nwell_tap connected directly or through a resistor to a Pad or to Vss/Vcc that is covered by areaid.ed and located within a double tap guardrings. Latch up rules
107 ESD_cascode_diffusion Diffusion covered by areaid.ed between two minimum spaced poly gates and located within a pair of double tap guardrings. (There should be no licons on the diffusion.) Latch up rules
108 ESD_diode Any nwell (other than ESD_nwell_tap ) covered by areaid.ed and areaid.de that does not contain poly Latch up rules
109 ESD_FET (any Pdiff covered by areaid:ed within a double tap guardrings) Or\nESD_NFET Latch up rules
110 ESD_NFET (any Ndiff covered by areaid:ed abutting ESD_nwell_tap) Or (any Ndiff covered by areaid:ed abutting gate within 3.5um of ESD_nwell_tap) Or (any Ndiff abutting ESD_nwell_tap within areaid.ed) a double tap guardrings Latch up rules
111 I/O_or_Output_Pmos ESD P+ diffusion overlapping poly and overlapping ESD source/drain diffusion connected to I/O or output net Latch up rules
112 I/O_Pmos_w/series_R ESD PMOS connected to I/O or output net through series resistors Latch up rules
113 met_ESD_resistor Metal resistor inside areaid:ed Latch up rules
114 Non_Vcc_nwell Any nwell connected to any bias other than power supply Latch up rules
115 Nwell_area Is determined using the following steps:\n(a) Grow pdiff by 1.5 mm\n(b) Merge\n(c) And Nwell:dg Latch up rules
116 Pwell_area Is determined using the following steps:\n(a) Grow ndiff by 1.5 mm\n(b) Merge\n(c) NOT Nwell:dg Latch up rules
117 Series_transistors Merged diffusion determined by Nwell_area and Pwell_area Latch up rules
118 fuse:dg met2:fe for S8D*/S8TM*, met3.fe for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*, met4.fe for S8P*/SP8P* Fuse rules
119 fuse_contact (fuse_metal overlapping fuse:dg) NOT fuse:dg Fuse rules
120 fuse_metal met3 for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*; met2 for S8D*/S8TM*, met4 for S8P*/SP8P* Fuse rules
121 fuse_shield Metal line (same metal level as fuse) between fuse and periphery, not overlapping contacts or vias, with specified dimensions Fuse rules
122 non-isolated fuse edge Long edge of the fuse spaced to Met2/Met3/Met4 less than a specified amount Fuse rules
123 single_fuses Fuses without neighboring fuses within specified distance Fuse rules

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waffle_chip ,icfb ver 5.0,icfb ver 5.1
drawing ,dg,drw
pin ,pn,pin
boundary ,by,bnd
net ,nt,net
res ,rs,res
label ,ll,lbl
cut ,ct,cut
short ,st,sho
pin ,pn,pin
gate ,ge,gat
probe ,pe,pro
blockage ,be,blo
model ,ml,mod
optionX (X = 1…n),oX (X = 1..n),opt*(X=1..n)
fuse ,fe,fus
mask ,mk,mas*
maskAdd ,md,mas*
maskDrop ,mp,mas*
waffleAdd1 ,w1,waffleAdd1
waffleAdd2 ,w2,waffleAdd2
waffleDrop ,wp,waf
error ,er,err
warning ,wg,wng
dummy ,dy,dmy
1 waffle_chip icfb ver 5.0 icfb ver 5.1
2 drawing dg drw
3 pin pn pin
4 boundary by bnd
5 net nt net
6 res rs res
7 label ll lbl
8 cut ct cut
9 short st sho
10 pin pn pin
11 gate ge gat
12 probe pe pro
13 blockage be blo
14 model ml mod
15 optionX (X = 1…n) oX (X = 1..n) opt*(X=1..n)
16 fuse fe fus
17 mask mk mas*
18 maskAdd md mas*
19 maskDrop mp mas*
20 waffleAdd1 w1 waffleAdd1
21 waffleAdd2 w2 waffleAdd2
22 waffleDrop wp waf
23 error er err
24 warning wg wng
25 dummy dy dmy

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waffle_chip,icfb ver 5.0,icfb ver 5.1,,,
drawing,dg,drw,,,
pin ,pn,pin,,,
boundary ,by,bnd,,,
net ,nt,net,,,
res ,rs,res,,,
label ,ll,lbl,,,
cut ,ct,cut,,,
short ,st,sho,,,
pin ,pn,pin,,,
gate ,ge,gat,,,
probe ,pe,pro,,,
blockage,be,blo,,,
model,ml,mod,,,
optionX (X = 1…n),oX (X = 1..n),opt*(X=1..n),,,
fuse,fe,fus,,,
mask ,mk,mas*,,,
maskAdd ,md,mas*,,,
maskDrop ,mp,mas*,,,
waffleAdd1 ,w1,waffleAdd1,,,
waffleAdd2 ,w2,waffleAdd2,,,
waffleDrop ,wp,waf,,,
error ,er,err,,,
warning ,wg,wng,,,
dummy,dy,dmy,,,
,,,,,
Layout Data Name & GDSII No.,Brief description,icfb ver 5.1,"Identifies\n(See WOLF-41, SPR 95111 for more details)",Who,Use
areaid.sl{81:1},areaid sealring,areaid.sea,The area of the Seal ring,Tech,
areaid.ww{81:13},areaid Waffle Window,areaid.waf,Used to prevent waffle shifting. When larger than areaid:sl re-defines the placement of waffles. ,Frame,CLDRC
areaid.dn{81:50},areaid dead Zon,areaid.dea,“deadzone” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks,Tech,
areaid.cr{81:51},areaid critCorner,areaid.cri*,For portions of layout that are not to be put in the critical side do to stress constraints. Should be used sparingly and only over the portion of the layout to remove DRC violations. Avoid using a blanket polygon over the entire layout. This layer is to be used instead of using the noCritSideReg verification option in Stress.\n“critical corner” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks,Tech,Stress
areaid.cd{81:52},areaid critSid,areaid.cri*,“criticalsid” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks,Tech,Stress
areaid.ce{81:2},areaid core,areaid.cor,Memory core (memory cells and approved on-pitch only),Tech,DRC
areaid.fe{81:3},areaid frame,areaid.fra*,Pads in the frame,Frame,DRC
areaid.ed{81:19},areaid ESD,areaid.esd,ESD devices- Surrounds any diffusion or ESD nwell tap connected to a signal pad. (only over ESD devices with special poly/tap exemption rules per LFL),"ESD, Des",DRC
areaid.dt{81:11},areaid die cut,areaid.die,"Location of the die within the frame used in frame builder \ngeneration to create blanking for die and other drop-ins. Also used in cldrc/drc for rules in frame to die edge (waffles, nsm, metals etc)",Frame,Tech
areaid.mt{81:10},areaid module cut,areaid.mod,Location of e-test modules within the frame used in frame builder generation to create data in scribe lane(example: opaque/clear masks) and to mark location of cells (etest and fab)for frame reports. Also used in drc/cldrc for rules to cell edge.,Frame,Tech
areaid.ft{81:12},areaid frameRect,areaid.fra*,Boundary of the frame used in frame builder generation to mark boundary of frame. Also used in cldrc/drc for rules to frame edge ,Frame,DRC/CLDRC
areaid.de{81:23},areaid Diode,areaid.dio,The area occupied by diodes; Used to identify diodes during LVS,All,LVS
areaid.sc{81:4},areaid standardc,areaid.sta,Cells in the standard cell library (over standard cell IP blocks only) .,Standard cell,DRC
areaid.st{81:53},areaid SubstrateCut,areaid.sub,"Regions to be considered as isolated substrates (only to designate 2 different resistively connected substrate \nregions, >100um apart)","Tech, Des, ESD","Latch up, LVS, soft"
areaid.en{81:57},areaid extended drain,areaid.ext,Used to identify the extended drain devices ,"Tech, Des, ESD",LVS
areaid.le{81:60},areaid LV Native,areaid.lvn,Used to identify the 3V Native NMOS versus 5V Native NMOS,"Tech, Des",LVS
areaid.po{81:81},areaid photo ,areaid.pho,The areaid id is to identify the dnwell photo diode,"Tech, Des",DRC
areaid.et{81:101},areaid etest,areaid.ete,Used in etest modules,Frame,DRC
areaid.ld{81:14},areaid low tap density,areaid.low,"6um tap to diff rule will not be checked in this region\nDiffusion >6u from related tap, requiring >50u from sigPadDiff && sigPadMetNtr).\nShould be used sparingly and only over the portion of the layout to remove DRC violations. This layer is not to be used if a tapping solution can be found. This layer can only be used if there is low risk for latchup. This layer will be reviewed during PDQC.",All,DRC
areaid.ns{81:15),areaid not-crtical side,areaid .not,"critSideReg stress rules will not be checked in this region\nCannot be placed in the critical side – uncommon, or where stress \nerrors can't be fixed)",All,DRC
areaid.ij{81:17},areaid injection,areaid.inj,Identify all circuits that are susceptible to injection and ensure no signal-pad connected diffusion is within 100u.\n“areaid.inj” encloses any circuitry deemed sensitive (by design team) to injected substrate areaid.inj encloses any PVT compliant circuitry,All,DRC
areaid.hl{81:63},areaid.hvnwell,areaid.hvn,"Identify nwell hooked to HV but containing FETs with thin oxide; \nPotential difference across the FET terminals is LV\nUsed over lv devices, operating in lv mode, placed in hv nwells, and should NOT have hvi",All,DRC
areaid.re{81:125},areaid rf diode,areaid.rfd,Defines rf diodes that need to be extracted with series resistance (memo GCZ-124/125),All,LVS
areaid.rd{81:24},areaid.rdlprobepad,areaid.rdl,Ignore RDL keepouts when opening up PMM2 ,All,CLDRC
areaid.sf{81:6},areaid sigPadDiff,,Identify all srdrn diffusions and tap which are intended to be \nconnected to signal pad (io Nets). Goes over diffusions connected to a signal pad - including through a poly resistor,All,LATCHUP
areaid.sl{81:7},areaid.sigPadWell,,"Identify all nwells and pwells which are intended to be connected to signal pad (io Nets). Goes over wells with tap connected to a signal pad, including through a poly resistor",All,LATCHUP
areaid.sr{81:8},areaid sigPadMetNtr,,"Identify all srcdrn, tap, and wells which are intended to be \nmetallically connected to signal pad (io Nets) not through a resistor. \nMust be used in unison with areaid.sigPadDifff or areaid.sigPadWell.\nUsed with one of the above 2 areaids, nodes metallically \nconnection to a sigPad (not through res)",All,LATCHUP
inductor:dg{82:24},ID layer for inductor,,Inductors,"Tech, Des",DRC
"t1,2,3 {82:26, 27, 28}",terminal labels for inductor,,Labels required by inductor terminals to be recognized as device,"Tech, Des",LVS
poly:ml {66:83},poly device model,,Model name extraction,"Tech, Des, ESD",LVS
ncm {92:44},N-Core Implant,,Ncm.dg is available as a drawn layer,All,DRC/CLDRC
protect),VPP capacitor,,"Interdigitated, vertical Li1, M1 and M2 capacitor ",All,LVS
capm_2t.dg,MIM caps (2 terminal model),,ID layer for MIMCAP that will be treated as 2T device,All,DRC/LVS
cpmm:dg{91},Drawn compatible polyimide layer,,Drawn compatible layer and used only inside S8 RF pad,Frame,
li1.be{67:10},li1 blockage layer,,Li1 blockage layer used for IP integration (per CWR 137),All,DRC
met1.be{68:10},Metal1 blockage layer,,Metal 1 blockage layer used for IP integration (per CWR 137),All,DRC
met2.be{69:10},Metal2 blockage layer,,Metal 2 blockage layer used for IP integration (per CWR 137),All,DRC
met3.be{70:10},Metal3 blockage layer,,Metal 3 blockage layer used for IP integration (per CWR 137),All,DRC
met4.be{71:10},Metal4 blockage layer,,Metal 4 blockage layer used for IP integration (per CWR 137),All,DRC
met5.be{72:10},Metal5 blockage layer,,Metal 5 blockage layer used for IP integration (per CWR 137),All,DRC
vhvi {74:21},Very High voltage id layer,,Used to identify nodes that operate at 12V nominal (16V max),Des,VHV Rules
uhvi {74:22},Ultra High voltage id layer,,Used to identify nodes that operate at 20V nominal,Des,UHV Rules
areaid.e0{81:58},Area extended drain,areaid.ext,Used to identify 20V drain extended devices,Des,LVS
areaid.zr{81:18},Area zener diode,areaid.zen,Used to identify Zener diodes,Des,LVS
fom.dy{},FOM dummy,,FOM waffle drawn in this layer,All,Waffles
prune:dg{84:44},prune,,Areas ignored by LVS ,Frame,LVS
areaid:cr {81:55},copper pillar (.cuPillar),areaid.cup,"Placement of Cu pillar over the pad area, streamed out to Amkor, s8pfhd-10r flow only",Die,CLDRC s8pfhd-10r
cyprotect.dg {56.44},External F25 layer,cyprotect.dg,Switch to direct streaming to drawn (no protect) or mask layer (with protect),Frame,CLDRC
cytextmc.dg {50:44},Locations for mask compose,cytextmc.dg,Text to extract placement for Fab25 tool,Frame,CLDRC
cypsbr.dg {51:44},No phaseshift allowed,cypsbr.dg,Phaseshift layer common to all F25 phaseshift masks,Frame,
areaid:ag{81:79},analog,areaid.ana,Used to identify analog circuits,All,Analog
natfet.dg {124:21},DEFETs,natfet.dg,"Add TUNM for SONOS channel implants. See SPR 117559, SGL-529",All,DRC/CLDRC
areaid:lw,Ultra High voltage id layer, ,Areaid low voltage: UHV box to put all HV/LV curcuits in,All,Analog
"* To distinguish the layers, the full name of the layer needs to be turned on in the LSW window",,,,,
"As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3"
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