Merge pull request #106 from mithro/res-cap
docs: Adding basic values for capacitance + resistance.
This commit is contained in:
Tim Ansell
GitHub
commit
107103f922
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@ -35,7 +35,7 @@ Devices and Layout vs Schematic (LVS) Information
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.. csv-table:: Table F2b: Mask Generation table
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:file: layers/table-f2b-mask.tsv
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:delim: "tab"
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:delim: U+0009
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:header-rows: 1
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:stub-columns: 1
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@ -59,7 +59,7 @@ Device and Layout vs. Schematic
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.. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS)
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:file: layers/table-f2a-lvs.tsv
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:delim: "tab"
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:delim: U+0009
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:header-rows: 1
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:stub-columns: 1
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@ -79,4 +79,4 @@ areaid:ag{81:79},analog,areaid.ana,Used to identify analog circuits,All,Analog
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natfet.dg {124:21},DEFETs,natfet.dg,"Add TUNM for SONOS channel implants. See SPR 117559, SGL-529",All,DRC/CLDRC
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areaid:lw,Ultra High voltage id layer, ,Areaid low voltage: UHV box to put all HV/LV curcuits in,All,Analog
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"* To distinguish the layers, the full name of the layer needs to be turned on in the LSW window",,,,,
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"As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3"
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"As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3",,,,,
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Can't render this file because it has a wrong number of fields in line 82.
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@ -8,9 +8,10 @@ The modeled columns indicate sheets and contacts that are parasitic resistance/c
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The CAD columns indicate sheets and contacts that are parasitics included in the schematic/layout RCX from Assura.
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.. csv-table:: Parasitic Extraction Table
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:file: rcx/rcx-all.csv
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:file: rcx/rcx-all.tsv
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:header-rows: 2
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:stub-columns: 1
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:delim: U+0009
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.. note:: The models includes M1/M2 capacitance. As a result of RCX extraction limitation M1/M2 routing over the varactor will have no capacitance extraction.
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@ -33,10 +34,21 @@ Resistance Rules
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.. todo:: This table should be rendered like the periphery rules.
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.. csv-table:: Table of resistance rules
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:file: rcx/resistance.csv
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:header-rows: 2
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:file: rcx/resistance-rules.csv
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:stub-columns: 1
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Resistance Values
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-----------------
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This section includes tables of basic resistance values for SKY130.
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Further data can be found in the `"SKY130 Stackup Capacitance Data" spreadsheet`_.
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.. csv-table:: Table - Resistances
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:file: rcx/resistance-values.tsv
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:header-rows: 1
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:delim: U+0009
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Capacitance Rules
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-----------------
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@ -44,11 +56,58 @@ Capacitance Rules
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.. todo:: This table should be rendered like the periphery rules.
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.. csv-table:: Table of capacitance rules
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:file: rcx/capacitance.csv
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:header-rows: 2
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:file: rcx/capacitance-rules.csv
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:stub-columns: 1
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Capacitance Values
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------------------
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This section includes tables of basic capacitance values for SKY130.
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Further data can be found in the `"SKY130 Stackup Capacitance Data" spreadsheet`_.
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.. _"SKY130 Stackup Capacitance Data" spreadsheet: https://docs.google.com/spreadsheets/d/1N9To-xTiA7FLfQ1SNzWKe-wMckFEXVE9WPkPPjYkaxE/edit#gid=226894802
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Basic Capacitance - Fringe Downward
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Fringe capacitances are a constant value per unit length and are an approximations. Determined by creating a layout with a 5um x 10um rectangle of each layer over or under a much larger rectangle of the other layer. The fringe capacitance computed from the total given minus the parallel plate capacitance.
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"downward direction" means that the larger plate is below the 5um x 10um plate.
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The layer in the first column is always the layer with the 5um x 10um plate.
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.. csv-table:: Table - Capacitance - Fringe Downward
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:file: rcx/capacitance-fringe-downward.tsv
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:header-rows: 1
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:delim: U+0009
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Basic Capacitance - Fringe Upward
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Fringe capacitances are a constant value per unit length and are an approximations. Determined by creating a layout with a 5um x 10um rectangle of each layer over or under a much larger rectangle of the other layer. The fringe capacitance computed from the total given minus the parallel plate capacitance.
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"upward direction" means that the larger plate is above the 5um x 10um plate.
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The layer in the first column is always the layer with the 5um x 10um plate.
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.. csv-table:: Table - Capacitance - Fringe Upward
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:file: rcx/capacitance-fringe-upward.tsv
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:header-rows: 1
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:delim: U+0009
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Basic Capacitance - Parallel
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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.. csv-table:: Table - Capacitance - Parallel
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:file: rcx/capacitance-parallel.tsv
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:header-rows: 1
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:delim: U+0009
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Discrepencies
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-------------
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@ -62,3 +121,4 @@ Un-shielded VPP's
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The impact of this on total capacitance and parasitic capacitance is already comprehended in the model corners, however, cross-talk is not modeled. Also, parasitic cap is routed to ground and this may not be ideal for the scenario.
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The parasitic cap can be estimated using RescapWeb.
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@ -0,0 +1,7 @@
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Interlayer fringe capacitance (downward direction) (aF/um) Poly Local interconnect Metal1 Metal2 Metal3 Metal4
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Local interconnect 51.846
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Metal1 46.724 59.496
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Metal2 41.222 46.277 67.045
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Metal3 43.531 46.708 54.814 69.846
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Metal4 38.105 39.709 42.563 46.382 70.522
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Metal5 39.908 41.147 43.188 45.592 54.152 82.819
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@ -0,0 +1,7 @@
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Interlayer fringe capacitance (upward direction) (aF/um) Local interconnect Metal1 Metal2 Metal3 Metal4 Metal5
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Poly 25.138 16.691 11.166 9.18 6.3505 6.4903
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Local interconnect 34.7 21.739 15.078 10.141 7.6366
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Metal1 48.193 26.676 16.421 12.017
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Metal2 44.432 22.332 15.693
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Metal3 42.643 27.836
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Metal4 46.976
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@ -0,0 +1,7 @@
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Interlayer parallel plate capacitance (aF/um^2) Local interconnect Metal1 Metal2 Metal3 Metal4 Metal5
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Poly 94.1644 44.8056 24.4968 16.0552 10.0131 7.2085
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Local interconnect 114.1970 37.5647 20.7915 11.6705 8.0265
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Metal1 133.8610 34.5350 15.0275 9.4789
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Metal2 86.1861 20.3321 11.3410
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Metal3 84.0346 19.6269
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Metal4 68.3252
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@ -1,30 +1,30 @@
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,General(CAP.-)
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.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.)
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,MOS Devices (MOS.-)
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.mos.1,area between poly and diff should not have capacitance extracted.
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.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8)
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.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).
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.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.
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,General (CAP.-),
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.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.),
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,,
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,MOS Devices (MOS.-),
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.mos.1,area between poly and diff should not have capacitance extracted.,
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.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8),
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.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).,
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.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.,
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.mos.5,All 20V NMOS ISO DEFETs will have the parasitic diode included in the models.,This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub).
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.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.
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.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.,
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.mos.7,The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor.,The model will over-write all other instance parameters from CAD extraction.
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,Resistors (RES.-)
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.res.1,short devices must not have capacitance calculated across the device.
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.res.2,fuse devices must have capacitance extracted.
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.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.
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.res.4,metops that are merged must have capacitance extracted.
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.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.
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.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).
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.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
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.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
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,Capacitors (PASSIVES.-)
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.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)"
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.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)"
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.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)"
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.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)"
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,Bipolar Devices
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,none
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,,
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,Resistors (RES.-),
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.res.1,short devices must not have capacitance calculated across the device.,
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.res.2,fuse devices must have capacitance extracted.,
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.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.,
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.res.4,metops that are merged must have capacitance extracted.,
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.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.,
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.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).,
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.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.",
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.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer.",
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,,
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,Capacitors (PASSIVES.-),
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.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)",
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.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)",
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.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)",
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.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)",
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,,
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,Bipolar Devices,
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,none,
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Can't render this file because it has a wrong number of fields in line 9.
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@ -1,26 +1,26 @@
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,General (RES.-)
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.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.
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,Sheet Resistance (SR.-)
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,General (RES.-),
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.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.,
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,,
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,Sheet Resistance (SR.-),
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.X,Calibre now extracts deltaW by bucketing the sheet rho based on different widths.,The accuracy of each bucket must be within 2% of the Sheet Rho Calc using deltaW.
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.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology)
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.met2,Parasitic resistance is calculated for all metal2.
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.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1
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.li1,Parasitic resistance is calculated for all li1.
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.poly.1,Parasitic resistance on gates is calculated to the center of the gate.
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.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.
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.diff.1,Parasitic resistance is not extracted for any diffusion regions.
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.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.
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.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.
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,contact-to-gate space (CT.-)
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.via,All vias will have parasitic resistance extracted.
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.mcon,All mcons will have parasitic resistance extracted.
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.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.
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.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.
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.licon.3,All licons that are connected to FETs will be extracted by RCX.
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.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.
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.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.
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.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.
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.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models."
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.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models."
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.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology),
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.met2,Parasitic resistance is calculated for all metal2.,
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.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1,
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.li1,Parasitic resistance is calculated for all li1.,
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.poly.1,Parasitic resistance on gates is calculated to the center of the gate.,
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.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.,
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.diff.1,Parasitic resistance is not extracted for any diffusion regions.,
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.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.,
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.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.,
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,,
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,contact-to-gate space (CT.-),
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.via,All vias will have parasitic resistance extracted.,
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.mcon,All mcons will have parasitic resistance extracted.,
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.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.,
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.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.,
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.licon.3,All licons that are connected to FETs will be extracted by RCX.,
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.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.,
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.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.,
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.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.,
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.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models.",
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.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models.",
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Can't render this file because it has a wrong number of fields in line 5.
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@ -0,0 +1,23 @@
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Layer Resistivity (mohms/sq)
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Poly 48200
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Local interconnect 12800
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Metal1 125
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Metal2 125
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Metal3 47
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Metal4 47
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Metal5 29
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Deep nwell 2200000
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Pwell (in deep nwell) 3050000
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Nwell 1700000
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N-diffusion 120000
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P-diffusion 197000
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HV N-diffusion 114000
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HV P-diffusion 191000
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XHR poly resistor 319800
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UHR poly resistor 2000000
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LICON contact 15000
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MCON contact 152000
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VIA 4500
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VIA2 3410
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VIA3 3410
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VIA4 380
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