Merge pull request #127 from mithro/more-docs
Adding more rule tables to the documentation.
This commit is contained in:
Tim Ansell
GitHub
commit
38a749752c
File diff suppressed because it is too large
Load Diff
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@ -7,6 +7,20 @@ SkyWater SKY130 Process Design Rules
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:maxdepth: 2
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rules/background
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rules/masks
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rules/assumptions
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rules/layers
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rules/summary
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rules/periphery
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rules/wlcsp
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rules/hv
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rules/antenna
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rules/rcx
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rules/errors
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@ -0,0 +1,85 @@
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Antenna Rules
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=============
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Antenna rules specify the maximum allowed ratio of interconnect area exposed to plasma etch to active gate poly area that is electrically connected to it when the interconnect is etched. Interconnect areas exposed to plasma etch are:
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* bottom areas of Licon, Mcon, Via, Via2
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* perimeter areas of connection layers Poly, Li, Met1, Met2, Met3
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Two types of checks are introduced in the following tables:
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* vertical for perimeter area, and
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* horizontal for contact area
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The numbers checked for are in the MAX_EGAR column.
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Definitions
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-----------
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.. csv-table:: Antenna Rules Definitions
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:file: antenna/definitions.csv
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:header-rows: 1
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:stub-columns: 1
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Antenna rule numbers depend on the connection to the following devices:
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pAntennaShort = (tap AndNot poly) AndNot nwell
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It is a p+ tap contact used to shortcut to substrate ground buses.
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AntennaDiode = (diff OR tap) AndNot (poly OR pAntennaShort)
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It is a reverse biased diode whose leakage current will discharge the interconnect area.
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These devices are not subject to LVS check and must not be reported in the schematic.
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Antenna rules are defined for the following ratio:
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When a diode is used
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``EGAR``
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Etch Gate Area Ratio = (EA / A_gate) - K x (AntennaDiode_area in um2) - diode_bonus [unitless]
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When diodes are not used
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``EGAR``
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Etch Gate Area Ratio = (EA / A_gate) [unitless]
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where:
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* ``K`` is a multiplying factor specified for each layer
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* ``AntennaDiode_area`` is the area of the AntennaDiode used to discharge the interconnect area exposed to plasma etch (should be 0 if no diode is used)
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The layout should satisfy the condition: ``EGAR`` <= ``MAX_EGAR``. The ``diode_bonus`` applies only when at least one diode is used, regardless from it's size.
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Tables
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------
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.. todo:: Most of these tables should be removed.
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.. csv-table:: Table Ia. Antenna rules (S8D*)
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:file: antenna/table-Ia-antenna-rules-s8d.csv
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:header-rows: 1
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:stub-columns: 1
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.. csv-table:: Table Ib. Antenna rules (S8TNV-5R)
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:file: antenna/table-Ib-antenna-rules-s8tnv-5r.csv
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:header-rows: 1
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:stub-columns: 1
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.. csv-table:: Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*)
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:file: antenna/table-Ic-antenna-rules-s8tm.csv
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:header-rows: 1
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:stub-columns: 1
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.. csv-table:: Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*)
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:file: antenna/table-Ie-antenna-rules-s8p.csv
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:header-rows: 1
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:stub-columns: 1
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.. csv-table:: Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*)
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:file: antenna/table-Ig-antenna-rules-s8p12.csv
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:header-rows: 1
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:stub-columns: 1
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@ -0,0 +1,9 @@
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Symbol,Explanation,Unit
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PI,Perimeter of Interconnect,um
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FLT,Final Layer thickness,um
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W,Width of MOS Transistor,um
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L,Length of MOS Transistor,um
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A,Area of MOS Transistor gate (= W x L),um2
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CA,Area of contact or via,um2
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SW,Sidewall area (= PI x FLT),um2
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EA,"Etched area (= CA for horizontal, = SW for vertical areas)",um2
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@ -0,0 +1,24 @@
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,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
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(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
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,,,,,,
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.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
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.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
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.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
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.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
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.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
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.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
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.pad.1,pad (via2 area/gate area),Horizontal,,6,36,n/a
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.indm.1,INDM (met3 perimeter area/gate area),Vertical,4.000,400,400,2200
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.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
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Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
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,,,,,,
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"Max length of Poly (approx, assumes min width)",,135,,n/a,,
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Max number of Licons,,103,,n/a,,
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"Max length of LI (approx, assumes min width)",,370,,2620,,
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Max number of Mcon,,103,,726,,
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"Max length of Met1 (approx, assumes min width)",,570,,4280,,
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Max number of Via,,266,,1866,,
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"Max length of Met2 (approx, assumes min width)",,570,,4280,,
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Max number of pad via,,4,,29,,
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"Max length of Met3 (approx, assumes min width)",,45,,370,,
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@ -0,0 +1,25 @@
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Table Ib. Antenna rules (S8TNV-5R),,,,,,
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,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
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(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
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,,,,,,
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.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
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.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
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.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
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.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
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.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
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.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
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.met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.850,400,400,2200
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.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
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Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
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,,,,,,
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"Max length of Poly (approx, assumes min width)",,135,,n/a,,
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Max number of Licons,,103,,n/a,,
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"Max length of LI (approx, assumes min width)",,370,,2620,,
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Max number of Mcon,,103,,726,,
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"Max length of Met1 (approx, assumes min width)",,570,,4280,,
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Max number of Via,,266,,1866,,
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"Max length of Met2 (approx, assumes min width)",,570,,4280,,
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Max number of Via2,,76,,535,,
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"Max length of Met3 (approx, assumes min width)",,230,,1760,,
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@ -0,0 +1,25 @@
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Table Ic. Antenna rules (S8TM-5R*/S8TMC-5R*/S8TMA-5R*),,,,,,
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,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
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(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
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,,,,,,
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.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
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.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
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.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
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.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
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.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
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.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
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.met3.1,Met3 (met3 perimeter area/gate area),Vertical,2.000,400,400,2200
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.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
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Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
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,,,,,,
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"Max length of Poly (approx, assumes min width)",,135,,n/a,,
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Max number of Licons,,103,,n/a,,
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"Max length of LI (approx, assumes min width)",,370,,2620,,
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Max number of Mcon,,103,,726,,
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"Max length of Met1 (approx, assumes min width)",,570,,4280,,
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Max number of Via,,266,,1866,,
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"Max length of Met2 (approx, assumes min width)",,570,,4280,,
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Max number of Via2,,9,,65,,
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"Max length of Met3 (approx, assumes min width)",,95,,740,,
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@ -0,0 +1,33 @@
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Table Ie. Antenna rules (S8P-5R/SP8P-5R/S8P-10R*),,,,,,
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,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
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(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
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,,,,,,
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.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
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.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
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.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
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.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
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.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
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.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
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.met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.800,400,400,2200
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via3.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
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met4.1,Met4 (met4 perimeter area/gate area),Vertical,0.800,400,400,2200
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via4.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
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waffle_chip,Met4 (met4 perimeter area/gate area),Vertical,2.000,400,400,2200
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.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
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Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
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,,,,,,
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"Max length of Poly (approx, assumes min width)",,135,,n/a,,
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Max number of Licons,,103,,n/a,,
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"Max length of LI (approx, assumes min width)",,370,,2620,,
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Max number of Mcon,,103,,726,,
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"Max length of Met1 (approx, assumes min width)",,570,,4280,,
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Max number of Via,,266,,1866,,
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"Max length of Met2 (approx, assumes min width)",,570,,4280,,
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Max number of Via2,,150,,1050,,
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"Max length of Met3 (approx, assumes min width)",,245,,1870,,
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Max number of Via3,,150,,1050,,
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"Max length of Met4 (approx, assumes min width)",,245,,1870,,
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Max number of Via4,,9,,65,,
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"Max length of Met5 (approx, assumes min width)",,95,,740,,
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@ -0,0 +1,33 @@
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Table Ig. Antenna rules (S8P12-10R*/S8PIR-10R/S8PF-10R*),,,,,,
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,Antenna ratios,Area checked: H/V,FLT,MAX_EGAR,,
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(ar_q.-.-),,,,Max EA/A w/o diode,K,Diode bonus
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,,,,,,
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.poly.1,Poly (poly perimeter area/gate area),Vertical,0.180,50,n/a,n/a
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.licon.1,Licon (licon1 area/gate area),Horizontal,,3,n/a,n/a
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.li.1,LI (LI perimeter area/gate area),Vertical,0.100,75,450,n/a
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.mcon.1,Mcon (mcon area/gate area),Horizontal,,3,18,n/a
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.met1.1,Met1 (met1 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via.1,Via (via area/gate area),Horizontal,,6,36,n/a
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.met2.1,Met2 (met2 perimeter area/gate area),Vertical,0.350,400,400,2200
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.via2.1,Via2 (via2 area/gate area),Horizontal,,6,36,n/a
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.met3.1,Met3 (met3 perimeter area/gate area),Vertical,0.800,400,400,2200
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via3.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
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met4.1,Met4 (met4 perimeter area/gate area),Vertical,0.800,400,400,2200
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via4.1,Via3 (via3 area/gate area),Horizontal,,6,36,n/a
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met5.1,Met4 (met4 perimeter area/gate area),Vertical,1.200,400,400,2200
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.ar.1,Antenna rules not checked for features connected to a pAntennaShort,,,,,
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Design limitations due to antenna rules (FET gate = 1um2).,,w/o diode,,with 1um2 diode,,
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,,,,,,
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"Max length of Poly (approx, assumes min width)",,135,,n/a,,
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Max number of Licons,,103,,n/a,,
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"Max length of LI (approx, assumes min width)",,370,,2620,,
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Max number of Mcon,,103,,726,,
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"Max length of Met1 (approx, assumes min width)",,570,,4280,,
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Max number of Via,,266,,1866,,
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"Max length of Met2 (approx, assumes min width)",,570,,4280,,
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Max number of Via2,,150,,1050,,
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"Max length of Met3 (approx, assumes min width)",,245,,1870,,
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Max number of Via3,,150,,1050,,
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"Max length of Met4 (approx, assumes min width)",,245,,1870,,
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Max number of Via4,,9,,65,,
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"Max length of Met5 (approx, assumes min width)",,165,,1240,,
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@ -8,4 +8,5 @@ criteria for GDS data.
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.. csv-table:: Table - Error Messages
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:file: errors.csv
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:header-rows: 1
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:stub-columns: 1
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:widths: 10, 10, 80
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@ -1,10 +0,0 @@
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SkyWater GDS Layers Information
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===============================
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The :download:`gds_layers.csv file <./gds_layers.csv>` provides a raw list of the
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layers used in the process with name, description and the GDS layer and data type.
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.. csv-table:: Table - GDS Layers
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:file: gds_layers.csv
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:header-rows: 1
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:widths: 10, 15, 10, 75
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@ -0,0 +1,237 @@
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High Voltage Methodology
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========================
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High Voltage is defined as a voltage outside the range of GND to Vcc. Any device that is subjected to a voltage outside the range of GND to Vcc is considered a high voltage device. These devices are subjected to special design rules and biasing conditions. The biasing conditions of these high voltage devices are detailed in the ETD.
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Failure Mechanisms in High Voltage Devices
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------------------------------------------
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The TDR have a special rules section for the layout and DRC of the high voltage (hv) device.
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These rules are framed so as to prevent the following failure mechanisms in circuits that use these devices:
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Transistor Performance Degradation under HV Gate Stress (Section 2.2.2 of EDR)
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The maximum voltage across the gate oxide (gate to channel voltage) is restricted to:
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a. Any HV NMOS device: 7.3 V @ 25C.
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b. Any HV PMOS device: 8.1 V @ 25C.
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|
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These voltages are not operating voltages, but points of failure.
|
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They should not be exceeded in any circuit at any time.
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Junction Leakage/breakdown
|
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The maximum source/drain to substrate junction voltages are restricted to the following:
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|
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a. Any HV NMOS device: 11.0 V @ 25C.
|
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b. Any HV PMOS device: 11.0 V @ 25C.
|
||||
|
||||
These voltages are not operating voltages, but points of failure.
|
||||
They should not be exceeded in any circuit at any time.
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|
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Gated-Diode Leakage/Breakdown
|
||||
All high voltage devices use 110A gate oxide thickness just like low voltage (0 to Vcc) devices.
|
||||
|
||||
The maximum gate-to-junction voltage differentials should be not exceed the voltage criteria set by conditions (1) and (2) above.
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||||
|
||||
In addition, hv p-channel devices are required to be laid out as ring devices (also called half-fieldless and fieldless devices), where the hv junction does not abut field oxide edge. These devices also get the extra junction grading implant into the ringed gate with the HVPDM mask.
|
||||
|
||||
Source to Drain Punch-through
|
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To prevent punch-through, the hv devices have expanded channel lengths:
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||||
|
||||
a. HV NMOS/PMOS device channel length = 0.500 um final.
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|
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Parasitic Isolation Field Leakage
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HV poly is prohibited from forming gates with adjacent hv diffusions, and from crossing well boundaries.
|
||||
|
||||
Exceptions to this rule are made only in cases where the bulk of the isolation device formed is back-biased by at least 300 mV.
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||||
|
||||
The presence of the back bias cannot be checked by the CAD flow at this time. Exceptions pass clean through DRC with the presence of the “hv_bb” tag on the hv poly.
|
||||
|
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The usage of the ``hv_bb`` tag is subject to approval by technology.
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||||
|
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Sub-threshold EndCap Leakage
|
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The extension of poly forming a high voltage gate onto field to prevent subthreshold leakage due to line-end shortening of the poly/field oxide endcap.
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||||
|
||||
|
||||
High Voltage Implementation Methodology
|
||||
---------------------------------------
|
||||
|
||||
Following are the features of the high voltage rules:
|
||||
|
||||
|
||||
High Voltage Diffusion (hvSRCDRN)
|
||||
The source of high voltage is a diffusion(source/drain) tagged within the high voltage identification layer diff:hv. The whole diffusion feature need to be completely enclosed by the diff:hv layer.
|
||||
|
||||
The source/drains that are tagged with the diff:hv layer are called taggedhvSRCDRN within the CAD flow code. The propagation of the high voltage property within the tagged piece of diffusion stops at a gate, i.e.. if tagging is done on the drain side, the source does not become a high voltage feature.
|
||||
|
||||
Beginning with taggedhvSRCDRN, high voltage propagates through standard interconnect to other SRCDRN or poly. Any SRCDRN derives the high voltage property through electrically shorting to a taggedhvSRCDRN is called a derivedhvSRCDRN within the CAD flow. Hence by definition, within the CAD flow,
|
||||
|
||||
hvSRCDRN = OR(taggedhvSRCDRN derivedhvSRCDRN)
|
||||
|
||||
``Rule hv.X.1`` (high voltage source/drain regions must be tagged by diff:hv) will check the presence of the diff:hv tag and flag on all derivedhvSRCDRN. When the layout is finally clean of all hv.diff.1 errors, hvSRCDRN will consist of only taggedhvSRCDRN (all derivedhvSRCDRN will need to be tagged with diff:hv to remove errors). This is shown in Fig.1.
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||||
|
||||
``Rule hv.diff.1`` (Minimum hv_source/drain spacing to diff for edges of hv_source/drain and diff not butting tap) prevents adjacent diffusions from punching through. Note that this rule specifies the spacing of a hvSRCDRN to any diffusion – be it another hvSRCDRN or a normal diffusion. This rule also applies to N+/P+ resistors that become hv by propagation. This is shown schematically in Fig.2.
|
||||
|
||||
``Rule hv.diff.2`` (P-channel hv_source/drain must be enclosed by a ring_FET gate) is required to prevent excess field oxide/gate edge leakage in high voltage p-channel devices (Fig.3). This ring_FET gate by definition is a hvring_FET (as it abuts hv diff).
|
||||
|
||||
High Voltage Poly (hvPoly)
|
||||
A high voltage poly feature (hvPoly) is defined as a poly feature which is electrically shorted to hvSRCDRN, or to another high voltage feature (like another hvPoly) through an interconnect. The whole poly feature becomes high voltage feature.
|
||||
|
||||
hvpoly propagates the high voltage property to other features which are electrically shorted (through licon1 & li1); but does not act as a source of high voltage. This means that hvpoly does not make underlying diffusions or wells high voltage – it acts as a “conductor” and propagates the high voltage property to other electrically connected features.
|
||||
|
||||
hvpoly cannot form parasitic field isolation devices, unless this device is back-biased. Hence, the following rules are in place:
|
||||
|
||||
``hv.poly.1``
|
||||
Hv poly feature can be drawn over only one diff region and is not allowed to cross nwell boundary except as allowed in rule hv.X.3. Please refer to Fig.4.
|
||||
|
||||
``hv.X.3``
|
||||
High voltage poly can be drawn over multiple diff regions that are ALL reverse-biased by at least 300 mV (existence of reverse-bias is not checked by the CAD flow).
|
||||
|
||||
In this case, the high voltage poly can be tagged with the ``text:dg`` label with a value “hv_bb”.
|
||||
|
||||
Exceptions to this use of the hv_bb label must be approved by technology.
|
||||
|
||||
Under certain bias conditions, high voltage poly tagged with hv_bb can cross an nwell boundary.
|
||||
|
||||
Use of the hv_bb label on high voltage poly crossing an nwell boundary must be approved by technology.
|
||||
|
||||
This is shown in Fig.5.
|
||||
|
||||
All high voltage poly tagged with hv_bb will not be checked to ``hv.poly.1``, ``hv.poly.2``, ``hv.poly.3`` and ``hv.poly.4``.
|
||||
|
||||
* ``hv.poly.2``: Spacing of hv poly on field to unrelated diff (Fig.6).
|
||||
* ``hv.poly.3``: Spacing of hv poly on field to n-well (Fig.6).
|
||||
* ``hv.poly.4``: Enclosure of hv poly on field by n-well (Fig.6).
|
||||
|
||||
Poly resistors can become high voltage features if the poly is electrically shorted to hvSRCDRN, or to another high voltage feature. Nevertheless, these devices cannot act as sources of hv, and the hv propagation stops at the edge of this device.
|
||||
|
||||
High Voltage Poly Gate (hvFET_gate)
|
||||
A high voltage poly gate (``hvFET_gate``) is a gate (``PolyAndDiff``) abutting hvSRCDRN. This is specified in rule ``hv.poly.8`` (Any poly gate abutting hv_source/drain becomes a high voltage poly gate).
|
||||
|
||||
Note that this is the only definition of a hvFET_gate and the only way a gate can become a hvFET_gate.
|
||||
|
||||
This is shown schematically in Fig.7.
|
||||
|
||||
The high voltage property of the ``hvFET_gate`` is limited to the gate only – the whole poly feature does not become a hvPoly.
|
||||
|
||||
The following rules are in place for hvFET_gates (please refer to Fig.12):
|
||||
|
||||
* ``hv.diff.2``: P-channel hv_source/drains must be enclosed by a ring_FET gate.
|
||||
This is required to prevent excess field oxide/gate edge leakage in high voltage p-channel devices.
|
||||
A p-channel hvring_FET gate is shown schematically in Fig.8.
|
||||
|
||||
* ``hv.poly.5``: Hv poly gate length (which is bigger than a normal gate length)
|
||||
|
||||
* ``hv.poly.6``: Extension of poly forming an ``hvFET_gate`` beyond hv diffusion
|
||||
|
||||
* ``hv.poly.7``: Minimum overlap of poly forming ``hvring_FET`` and diffusion
|
||||
|
||||
Stoppers to High Voltage Propagation
|
||||
The following act as stoppers for hv propagation (shown in Fig.10):
|
||||
|
||||
* For a ``hv_source``/``drain`` tagged with ``diff:hv``, the high voltage property terminates at the intersection of this hv diff with a poly, i.e. at the gate edge. This means that one side of the device can have a hv diff, while the other side of the gate can remain low voltage.
|
||||
|
||||
* N+/P+ diffusion resistors are allowed per the Allowed Resistors table in the TDR. These resistors do not originate high voltage. They also do not propagate high voltage, although the device itself becomes a high voltage device. The hv rule hv.diff.1 needs to be checked for these devices.
|
||||
|
||||
* Diodes do not originate high voltage. Nevertheless, they propagate high voltage and become high voltage devices when high voltage is propagated to them. The hv rule hv.diff.1 needs to be checked for these devices.
|
||||
|
||||
* A poly forming a poly resistor can become hvPoly by virtue of shorting to a hv_source/drain or shorting to another high voltage feature through an interconnect. The high voltage propagation stops at a poly resistor, although the device itself becomes high voltage. This device will be checked to the following hv rules: hv.poly.1, hv.poly.2, hv.poly.3, and hv.poly.4. These rule checks can be exempted by the use of the "hv_bb" tag with the approval of technology.
|
||||
|
||||
* The high voltage propagation also stops at a P-Well resistor. The device becomes a hv device. There are no specific rule checks for this hv device.
|
||||
|
||||
Summary of High Voltage Propagation
|
||||
The high voltage propagation methodology is summarized below in Table 1.
|
||||
|
||||
A test case utilizing the outlined methodology is shown in Fig.12.
|
||||
|
||||
|
||||
.. csv-table:: Table 1. Truth table for high voltage generation, propagation and retention.
|
||||
:file: hv/table-1.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. include:: hv/table-1-key.rst
|
||||
|
||||
|
||||
Very High Voltage Methodology
|
||||
=============================
|
||||
|
||||
Very High Voltage is defined as a voltage outside the range of GND to High Voltage (11V). Very high voltage is 16V (12V nominal) Vcc.
|
||||
|
||||
Any device that is subjected to a voltage outside the range of GND to 11V is considered a Very High Voltage (VHV) device.
|
||||
|
||||
These devices are subjected to special design rules and biasing conditions.
|
||||
|
||||
|
||||
Failure Mechanisms in VHV Devices
|
||||
---------------------------------
|
||||
|
||||
The TDR have a special rules section for the layout and DRC of the VHV device.
|
||||
|
||||
These rules are framed so as to prevent the following failure mechanisms in
|
||||
circuits that use these devices:
|
||||
|
||||
Transistor Performance Degradation under VHV Gate Stress
|
||||
The maximum voltage across the gate oxide (gate to channel voltage) is restricted to:
|
||||
|
||||
a. Any VHV NMOS device: 5.5V.
|
||||
b. Any VHV PMOS device: 5.5V.
|
||||
|
||||
Junction Leakage/breakdown
|
||||
The maximum source/drain to substrate junction voltages are restricted to the following:
|
||||
|
||||
a. Any VHV NMOS device: 16.0V.
|
||||
b. Any VHV PMOS device: 16.0V.
|
||||
|
||||
Gated-Diode Leakage/Breakdown:
|
||||
All VHV devices use 110A gate oxide thickness just like standard 5.0V Vcc devices.
|
||||
|
||||
The maximum gate-to-junction voltage differentials should not exceed the voltage criteria set by conditions (1) and (2) above.
|
||||
|
||||
The VHV devices need to be designed with drain extentions (DE) fabricated by lightly doped Nwells and Pwellsrespectively. Under no circumstances the poly/extended drain overlap and field oxide length should be changed.
|
||||
|
||||
Source to Drain Punch-through
|
||||
To prevent punch-through, the VHV devices have expanded channel lengths:
|
||||
|
||||
a. VHV NMOS device channel length = 1.055 um drawn.
|
||||
b. VHV PMOS device channel length = 1.050 um drawn.
|
||||
|
||||
Parasitic Isolation Field Leakage
|
||||
Poly from a drain extended device is prohibited from forming gates with adjacent hv diffusions.
|
||||
|
||||
|
||||
Sub-threshold EndCap Leakage
|
||||
The extension of poly forming a high voltage gate onto field to prevent subthreshold leakage due to line-end shortening of the poly/field oxide endcap.
|
||||
|
||||
Reliability performance:
|
||||
In order to preserve the reliability performance of the VHV FETs the Field Oxide (STI) length may not be changed from the values below:
|
||||
|
||||
a. VHV NMOS STI length = 1.585 um
|
||||
b. VHV PMOS STI length = 1.190 um
|
||||
|
||||
A poly gate may never be directly connected to a VHV diffusion region.
|
||||
|
||||
Poly connecting two VHV nodes over field must be routed through LI or metal.
|
||||
|
||||
VHV Implementation Methodology
|
||||
------------------------------
|
||||
|
||||
Following are the features of the VHV rules:
|
||||
|
||||
* All features operating at 16V (max) voltages can be Very-High-Voltage (VHV)
|
||||
|
||||
* Drain or source of the drain-extended device can be tagged with vhvi:dg layer. Device with either drain or source (not both) tagged with vhvi:dg layer serves as propagation stopper
|
||||
|
||||
* The VHVSourceDrain can be connected to another VHVSourceDrain or an output pad. The VHVSourceDrain does not propagate the VHV through the device
|
||||
|
||||
* All source/drains/gate tagged with vhvi:dg propagate VHV through any interconnects.
|
||||
|
||||
* Diff inside areaid.ed on the same net as VHVSourceDrain should be tagged with vhvi:dg. They serve as propagation stopper.
|
||||
|
||||
* Deep N-well, N-well, P-well, Diff, or Poly cannot be used as routing layers.
|
||||
|
||||
.. csv-table:: Table 2 - Truth table for very high voltage generation, propagation and retention.
|
||||
:file: hv/table-2.csv
|
||||
:header-rows: 1
|
||||
|
||||
.. include:: hv/table-2-key.rst
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
.. rubric:: Footnotes
|
||||
|
||||
.. [#f1] Deep N-Wells, N-Wells and P-Wells cannot be used as routing layers.
|
||||
.. [#f2] No hv rule checks for this device.
|
||||
.. [#f3] For N+ and P+ diffusion resistors and diodes, rule hv.diff.1 (spacing to unrelated diff) needs to be checked.
|
||||
.. [#f4] Need to be checked for hv.poly.1, hv.poly.2, hv.poly.3, hv.poly.4. Needs technology approval for use of hv.X.3.
|
||||
.. [#f5] The hv property is localized to the hvgate and its extensions.
|
||||
.. [#f6] Interconnect and contacts propagate hv, and are hv devices internal to the CAD flow only.
|
||||
.. [#f7] "N/A" implies that there are no special hv rules for these layers.
|
||||
|
|
@ -0,0 +1,21 @@
|
|||
Node Type,Originates HV?,Propagates HV?,Becomes HV? (when HV Propagates to this node),Notes
|
||||
Deep N-Well,No,N/A,N/A,"[#f1]_ [#f7]_"
|
||||
P-Well,No,N/A,N/A,"[#f1]_ [#f7]_"
|
||||
P-Well Resistor,No,No,Yes,[#f2]_
|
||||
N-Well,No,N/A,N/A,"[#f1]_ [#f7]_"
|
||||
waffle_chip,No,Yes,Yes,
|
||||
P+ Diffusion,No,Yes,Yes,
|
||||
N+ Diffusion Resistor,No,No,Yes,[#f3]_
|
||||
P+ Diffusion Resistor,No,No,Yes,[#f3]_
|
||||
HV Diffusion,Yes,Yes,Yes,
|
||||
Diodes,No,Yes,Yes,[#f3]_
|
||||
Poly,No,Yes,Yes,
|
||||
Poly Resistor,No,No,Yes,[#f4]_
|
||||
GATE,No,No,No,
|
||||
HvFET_gate (GATE abutting hv Diff),No,No,Yes,[#f5]_
|
||||
Licon1,No,Yes,N/A,[#f6]_
|
||||
Li1,No,Yes,N/A,[#f6]_
|
||||
Mcon,No,Yes,N/A,[#f6]_
|
||||
Met1,No,Yes,N/A,[#f6]_
|
||||
Via,No,Yes,N/A,[#f6]_
|
||||
Met2,No,Yes,N/A,[#f6]_
|
||||
|
|
|
@ -0,0 +1,4 @@
|
|||
.. rubric:: Footnotes
|
||||
|
||||
.. [#f8] Resistors tagged with text ""vhv_block"" serve as VHV propagation stopper and it is the duty of the designer to ensure that the resistor can support the required voltage drop. Otherwise components in VHV nets need to be tagged with vhvi:dg layer
|
||||
.. [#f9] If only source or drain is tagged with vhvi:dg layers.
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
Node Type,Originates VHV?,Propagates VHV?,Requires tagging with vhvi:dg (flags if not tagged when required)
|
||||
Deep N-Well,No,N/A,N/A
|
||||
P-Well,No,N/A,N/A
|
||||
P-Well Resistor,No,No [#f8]_ ,Yes
|
||||
N-Well,No,N/A,N/A
|
||||
LV Diffusion,No,Yes,Yes
|
||||
Diffusion Resistor,No,No [#f8]_ ,Yes
|
||||
HV Diffusion,No,Yes,Yes
|
||||
VHV ESD Diffusion,No,No,Yes
|
||||
VHVSourceDrain,Yes,No [#f9]_ ,Yes
|
||||
Diodes,No,Yes,Yes
|
||||
Poly,No,N/A,N/A
|
||||
Poly Resistor,No,No [#f8]_ ,Yes
|
||||
VHVPoly,Yes,Yes,Yes
|
||||
GATE,No,N/A,N/A
|
||||
de_pFET_gate,No,N/A,N/A
|
||||
de_nFET_gate,No,N/A,N/A
|
||||
Licon1,No,Yes,No
|
||||
Li1,No,Yes,No
|
||||
Mcon,No,Yes,No
|
||||
Met1,No,Yes,No
|
||||
Via,No,Yes,No
|
||||
Met2,No,Yes,No
|
||||
via2,No,Yes,No
|
||||
Met3,No,Yes,No
|
||||
|
|
|
@ -0,0 +1,65 @@
|
|||
Layers Reference
|
||||
================
|
||||
|
||||
Layers Definitions
|
||||
------------------
|
||||
|
||||
.. csv-table:: Table C3: Device, LVS and other CAD definitions
|
||||
:file: layers/table-c3-device-lvs-other.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
Auxiliary Layers
|
||||
----------------
|
||||
|
||||
.. csv-table:: Table C4a: Purpose layer description in LSW window and Auxiliary Layers
|
||||
:file: layers/table-c4a-layer-description.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. csv-table:: Table C4b: Purpose layer description in LSW window and Auxiliary Layers
|
||||
:file: layers/table-c4b-layer-description.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
Devices and Layout vs Schematic (LVS) Information
|
||||
-------------------------------------------------
|
||||
|
||||
.. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS)
|
||||
:file: layers/table-c4b-layer-description.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. include:: layers/table-f2a-lvs-key.rst
|
||||
|
||||
|
||||
.. csv-table:: Table F2b: Mask Generation table
|
||||
:file: layers/table-f2b-mask.tsv
|
||||
:delim: "tab"
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. include:: layers/table-f2b-mask-key.rst
|
||||
|
||||
|
||||
GDS Layers Information
|
||||
----------------------
|
||||
|
||||
The :download:`gds_layers.csv file <./gds_layers.csv>` provides a raw list of the
|
||||
layers used in the process with name, description and the GDS layer and data type.
|
||||
|
||||
.. csv-table:: Table - GDS Layers
|
||||
:file: gds_layers.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
:widths: 10, 15, 10, 75
|
||||
|
||||
Device and Layout vs. Schematic
|
||||
===============================
|
||||
|
||||
.. csv-table:: Table F2a: Devices and Layout vs. Schematic (LVS)
|
||||
:file: layers/table-f2a-lvs.tsv
|
||||
:delim: "tab"
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
|
|
@ -0,0 +1,123 @@
|
|||
Name,Defining algorithm,,,Used in …
|
||||
AR_met2_A,Net Area Ratio of met2 not connected to via and of via2 >=0.05 [Equation: (AREA(via2))/(2 * AREA(met2NotConnVia) + PERIMETER(met2NotConnVia) * 0.35)],,,Rules
|
||||
AR_met2_B,"Net Area Ratio of met2GroundOrFloat, via, and via2 <=0.032 [Equation: (AREA(via2))/(2 * AREA(met2GroundOrFloatVia) + PERIMETER(met2GroundOrFloatVia) * 0.35)]",,,Rules
|
||||
bondPad,pad:dg OUTSIDE areaid:ft,,,Rules
|
||||
bottom_plate,(capm:dg AND met2:dg) sized by capm.3; Exclude all capm sharing same metal2 plate,,,Rules
|
||||
Capacitor,Capm enclosing at least one via2,,,Rules
|
||||
Chip_extent,Holes (areaid:sl ) OR areaid.sl,,,Rules
|
||||
Diecut_pmm,areaid.dt NOT (cfom.wp OR cp1m.wp OR cmm1.wp OR cmm2.wp),,,Rules
|
||||
drain_diffusion,(diff NOT poly in nwell or pwell) not abutting tap in the same well or abutting tap in the opposite well,,,Rules
|
||||
dummy_capacitor,Capm not overlapping via2,,,Rules
|
||||
dummy_poly,"poly overlapping text ""dummy_poly"" (written using text.dg)",,,Rules
|
||||
ESD_nwell_tap,"n+ tap coincident with nwell such that n+ tap and nwell are completely surrounded by and abutting n+ diff on all edges, within areaid:ed ",,,Rules
|
||||
fomDmy_keepout_1, (diff.dg OR tap.dg OR poly.dg OR pwell resistor OR pad OR cfom.dg OR cfom.mk OR PhotoArray OR cp1m.mk),,,Rules
|
||||
floating_met*,met*.dg not connected to diffusion or tap through met(*+1) or met(*-1) and their respecitve vias and contacts,,,Rules
|
||||
fom_waffles,"fom.mk with dimensions (um x um): 0.5 x 0.5, 1.5 x 1.5, 2.5 x 2.5 and 4.08 x 4.08",,,Rules
|
||||
gated_npn,cell name: s8rf_npn_1x1_2p0_HV,,,Rules
|
||||
huge_metX,Metal X geometry wider and longer than 3.000um,,,Rules
|
||||
hugePad,pad.mk with width > 100um,,,Rules
|
||||
iso_pwell,(NOT nwell) AND dnwell,,,Rules
|
||||
isolated_tap,tap that does not abut diff,,,Rules
|
||||
laser_target,cell *lazX_* and *lazY_* OUTSIDE areaid:ft,,,Rules
|
||||
LVnwell,nwell NOT hvi,,,Rules
|
||||
LVTN_Gate,Gate overlapping lvtn,,,Rules
|
||||
met2GroundOrFloat,met2 connected to ptap or met2 not connected to difftap\n,,,Rules
|
||||
met2GroundOrFloatVia,met2GroundOrFloat interacting with via2 >2,,,Rules
|
||||
N+_diff,Diff NOT Nwell,,,Rules
|
||||
N+_tap,Tap AND Nwell,,,Rules
|
||||
nsdmHoles,Hole( nsdm ),,,Rules
|
||||
NSM_keepout,nsm.dg OR nsm.mk,,,Rules
|
||||
nwell_all,nwell OR extension of cnwm beyond nwell edge straddling de_nFet_source by cnwm.3f (45 degree edges are retained for the NVHV device nwell); Rule cnwm.3f applies only to GSMC flows,,,Rules
|
||||
P+_diff,Diff AND Nwell,,,Rules
|
||||
P+_tap,Tap NOT Nwell,,,Rules
|
||||
Pattern_density,(diff_tap area) / PD window (as specified in the rule section),,,Rules
|
||||
photoDiode,deep nwell overlapping areaid.po. Die+frame utility will use the mask data of dnwell in the implementation of this definition,,,Rules
|
||||
poly_licon1,Any licon1 that does not overlap ((diff or tap) NOT poly),,,Rules
|
||||
poly_waffles,"p1m.mk with dimensions (um x um): 0.48 x 0.48, 0.54 x 0.54 and 0.72 x 0.72",,,Rules
|
||||
prec_resistor,rpm AND (poly overlapping poly.rs) AND psdm,,,Rules
|
||||
prec_resistor_terminal,prec_resistor AND li,,,Rules
|
||||
psdmHoles,Hole( psdm ),,,Rules
|
||||
pwell,NOT nwell (default substrate area),,,Rules
|
||||
pwres_terminal,P+tap abutting pwell.rs,,,Rules
|
||||
pnp_emitter,diff AND pnp.dg AND psdm,,,Rules
|
||||
routing_terminal,metX.pin sized inside of metX.drawing by 1/2 * metalX min width; Similar defintion applies to Li1 layer,,,Rules
|
||||
scribe_line,areaid:ft NOT areaid:dt,,,Rules
|
||||
slotted_licon,licon1.dg of size 0.19um x 2.0um,,,Rules
|
||||
slotted_licon_edge1,2.0um edge of the slotted_licon,,,Rules
|
||||
source_diffusion,(diff NOT poly in nwell or pwell) abutting tap in same well,,,Rules
|
||||
tap_licon,Tap AND Licon1,,,Rules
|
||||
tap_notPoly,tap NOT poly,,,Rules
|
||||
top_indmMetal,met3 for S8D*,,,Rules
|
||||
top_metal,met3.dg OR mm3.mk (for S8T*/SP8TEE-5R); met3.dg OR indm.mk (for S8D*); met4.dg OR mm4.mk (for SP8Q/S8Q*); met5.dg OR mm5.mk (for SP8P*/S8P*),,,Rules
|
||||
top_padVia,Via2 for S8D*,,,Rules
|
||||
top_plate,capm:dg,,,Rules
|
||||
Var_channel,poly AND tap AND (nwell NOT hvi) NOT areaid.ce,,,Rules
|
||||
VaracTap,Tap overlapping Var_channel,,,Rules
|
||||
vpp_with_noLi,vpp with cell names: FIXME,,,Rules
|
||||
vpp_with_Met3Shield,vpp with cell names: FIXME,,,Rules
|
||||
vpp_with_LiShield,vpp with cell names: FIXME,,,Rules
|
||||
vpp_over_MOSCAP,"vpp with cell names: FIXME when over nhvnative W/L=10x4, FIXME when over phv/pshort/phighvt/plowvt W/L=5x4",,,Rules
|
||||
vpp_with_Met5PolyShield,vpp with cell names: FIXME,,,Rules
|
||||
vpp_with_Met5,vpp with cell names: FIXME,,,Rules
|
||||
cp1m_HV,cp1m AND Hvi,,,Rules (HV)
|
||||
de_nFet_drain,((isolated tap) AND areaid.en) overlapping nwell,,,Rules (HV)
|
||||
de_nFET_gate,deFET_gate overlapping (diff NOT dnwell),,,Rules (HV)
|
||||
de_nFet_source,(diff AND areaid.en) overlapping de_nFET_gate,,,Rules (HV)
|
||||
de_pFet_drain,((isolated tap) AND areaid.en) not overlapping nwell,,,Rules (HV)
|
||||
de_pFET_gate,deFET_gate overlapping (diff AND dnwell),,,Rules (HV)
|
||||
de_pFet_source,(diff AND areaid.en) overlapping de_pFET_gate,,,Rules (HV)
|
||||
deFET_gate,"(poly AND areaid.en) not overlapping pwm ; For CAD flows that do not have pwm layer, it is (poly AND areaid.en)",,,Rules (HV)
|
||||
Hdiff,Diffusion AND Hvi,,,Rules (HV)
|
||||
Hgate,Hpoly AND diff,,,Rules (HV)
|
||||
Hnwell,Nwell AND Hvi,,,Rules (HV)
|
||||
Hpoly,Poly AND Hvi,,,Rules (HV)
|
||||
Htap,Tap AND Hvi,,,Rules (HV)
|
||||
hv_source/drain,= (diff andNot poly) that overlaps diff.hv,,,Rules (HV)
|
||||
hvFET_gate,= FET_gate butting hv_source/drain,,,Rules (HV)
|
||||
hvPoly,= poly electrically connected to hv_source/drain,,,Rules (HV)
|
||||
HV_nwell,(nwell AND hvi) OR (nwell overlapping areaid.hl),,,Rules (HV)
|
||||
stack_hv_lv_diff,(diff And Hvi NOT nwell) abutting (diff NOT nwell),,,Rules (HV)
|
||||
SHVdiff,Diff And shvi,,,Rules (SHV)
|
||||
SHVGate,SHVPoly AND diff,,,Rules (SHV)
|
||||
SHVPoly,Poly OVERLAP shvi:dg,,,Rules (SHV)
|
||||
SHVSourceDrain,Diff And shvi NOT poly NOT diff:rs,,,Rules (SHV)
|
||||
VHVdiff,Diff And vhvi,,,Rules (VHV)
|
||||
VHVGate,VHVPoly AND diff,,,Rules (VHV)
|
||||
VHVPoly,Poly OVERLAP vhvi:dg,,,Rules (VHV)
|
||||
VHVSourceDrain,(Diff AND tap) And vhvi NOT poly NOT diff:rs,,,Rules (VHV)
|
||||
background,"Area where waffling grid is defined, sized to avoid waffle shift between runs",,,Waffles
|
||||
die,Holes (areaid:sl ),,,Waffles
|
||||
frame,( areaid.ft SIZE by -(max of s.2e/h)) NOT (OR areaid.dt SEALIDandHole),,,Waffles
|
||||
inductor_metal,(inductor:dg AND (met1 OR met2 OR met3)) size by 10 um [For all flows except S8PIR-10R]\ninductor.dg [for the S8PIR-10R flow],,,Waffles
|
||||
mm*_slot,mm* slots are defined as empty holes in metal that are located in (areaid.cr OR areaid.cd),,,Waffles
|
||||
nwellDnwellHoles,(inner HOLES of nwellAndDnwell). Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition,,,Waffles
|
||||
photoArray,(OR nwellAndDnwell nwellDnwellHoles) enclosing photoDiode. Die+frame utility will use the mask data of nwell and dnwell in the implementation of this definition,,,Waffles
|
||||
gate,poly AND diff,,,"pfet, nfet (LVS)"
|
||||
nfet,Gate NOT nwell,,,"pfet, nfet (LVS)"
|
||||
pfet,Gate AND nwell,,,"pfet, nfet (LVS)"
|
||||
nDiode,Ndiff AND DiodeID,,,Diodes (LVS)
|
||||
Pdiff,diff AND nwell,,,Diodes (LVS)
|
||||
pDiode,Pdiff AND DiodeID,,,Diodes (LVS)
|
||||
diff_hole,Hole( diff ),,,ESD (LVS)
|
||||
diff_tap_nwell,tap_nwell INSIDE diff_hole,,,ESD (LVS)
|
||||
esd_diff_tap_nwell,ESDID AND diff_tap_nwell,,,ESD (LVS)
|
||||
Ndiff,diff NOT nwell,,,ESD (LVS)
|
||||
tap_nwell,tap INSIDE nwell,,,ESD (LVS)
|
||||
ESD_diffusion,A+B31ny diffusion or ESD_nwell_tap connected directly or through a resistor to a Pad or to Vss/Vcc that is covered by areaid.ed and located within a double tap guardrings.,,,Latch up rules
|
||||
ESD_cascode_diffusion,Diffusion covered by areaid.ed between two minimum spaced poly gates and located within a pair of double tap guardrings. (There should be no licons on the diffusion.),,,Latch up rules
|
||||
ESD_diode,Any nwell (other than ESD_nwell_tap ) covered by areaid.ed and areaid.de that does not contain poly,,,Latch up rules
|
||||
ESD_FET,(any Pdiff covered by areaid:ed within a double tap guardrings) Or\nESD_NFET,,,Latch up rules
|
||||
ESD_NFET,(any Ndiff covered by areaid:ed abutting ESD_nwell_tap) Or (any Ndiff covered by areaid:ed abutting gate within 3.5um of ESD_nwell_tap) Or (any Ndiff abutting ESD_nwell_tap within areaid.ed) a double tap guardrings,,,Latch up rules
|
||||
I/O_or_Output_Pmos,ESD P+ diffusion overlapping poly and overlapping ESD source/drain diffusion connected to I/O or output net,,,Latch up rules
|
||||
I/O_Pmos_w/series_R,ESD PMOS connected to I/O or output net through series resistors,,,Latch up rules
|
||||
met_ESD_resistor,Metal resistor inside areaid:ed,,,Latch up rules
|
||||
Non_Vcc_nwell,Any nwell connected to any bias other than power supply,,,Latch up rules
|
||||
Nwell_area,Is determined using the following steps:\n(a) Grow pdiff by 1.5 mm\n(b) Merge\n(c) And Nwell:dg,,,Latch up rules
|
||||
Pwell_area,Is determined using the following steps:\n(a) Grow ndiff by 1.5 mm\n(b) Merge\n(c) NOT Nwell:dg,,,Latch up rules
|
||||
Series_transistors,Merged diffusion determined by Nwell_area and Pwell_area,,,Latch up rules
|
||||
fuse:dg,"met2:fe for S8D*/S8TM*, met3.fe for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*, met4.fe for S8P*/SP8P*",,,Fuse rules
|
||||
fuse_contact,(fuse_metal overlapping fuse:dg) NOT fuse:dg,,,Fuse rules
|
||||
fuse_metal,"met3 for S8TEE*/S8TNV/S8Q*/SP8TEE-5R/SP8Q*; met2 for S8D*/S8TM*, met4 for S8P*/SP8P*",,,Fuse rules
|
||||
fuse_shield,"Metal line (same metal level as fuse) between fuse and periphery, not overlapping contacts or vias, with specified dimensions",,,Fuse rules
|
||||
non-isolated fuse edge,Long edge of the fuse spaced to Met2/Met3/Met4 less than a specified amount,,,Fuse rules
|
||||
single_fuses,Fuses without neighboring fuses within specified distance,,,Fuse rules
|
||||
|
|
|
@ -0,0 +1,25 @@
|
|||
waffle_chip ,icfb ver 5.0,icfb ver 5.1
|
||||
drawing ,dg,drw
|
||||
pin ,pn,pin
|
||||
boundary ,by,bnd
|
||||
net ,nt,net
|
||||
res ,rs,res
|
||||
label ,ll,lbl
|
||||
cut ,ct,cut
|
||||
short ,st,sho
|
||||
pin ,pn,pin
|
||||
gate ,ge,gat
|
||||
probe ,pe,pro
|
||||
blockage ,be,blo
|
||||
model ,ml,mod
|
||||
optionX (X = 1…n),oX (X = 1..n),opt*(X=1..n)
|
||||
fuse ,fe,fus
|
||||
mask ,mk,mas*
|
||||
maskAdd ,md,mas*
|
||||
maskDrop ,mp,mas*
|
||||
waffleAdd1 ,w1,waffleAdd1
|
||||
waffleAdd2 ,w2,waffleAdd2
|
||||
waffleDrop ,wp,waf
|
||||
error ,er,err
|
||||
warning ,wg,wng
|
||||
dummy ,dy,dmy
|
||||
|
|
|
@ -0,0 +1,82 @@
|
|||
waffle_chip,icfb ver 5.0,icfb ver 5.1,,,
|
||||
drawing,dg,drw,,,
|
||||
pin ,pn,pin,,,
|
||||
boundary ,by,bnd,,,
|
||||
net ,nt,net,,,
|
||||
res ,rs,res,,,
|
||||
label ,ll,lbl,,,
|
||||
cut ,ct,cut,,,
|
||||
short ,st,sho,,,
|
||||
pin ,pn,pin,,,
|
||||
gate ,ge,gat,,,
|
||||
probe ,pe,pro,,,
|
||||
blockage,be,blo,,,
|
||||
model,ml,mod,,,
|
||||
optionX (X = 1…n),oX (X = 1..n),opt*(X=1..n),,,
|
||||
fuse,fe,fus,,,
|
||||
mask ,mk,mas*,,,
|
||||
maskAdd ,md,mas*,,,
|
||||
maskDrop ,mp,mas*,,,
|
||||
waffleAdd1 ,w1,waffleAdd1,,,
|
||||
waffleAdd2 ,w2,waffleAdd2,,,
|
||||
waffleDrop ,wp,waf,,,
|
||||
error ,er,err,,,
|
||||
warning ,wg,wng,,,
|
||||
dummy,dy,dmy,,,
|
||||
,,,,,
|
||||
Layout Data Name & GDSII No.,Brief description,icfb ver 5.1,"Identifies\n(See WOLF-41, SPR 95111 for more details)",Who,Use
|
||||
areaid.sl{81:1},areaid sealring,areaid.sea,The area of the Seal ring,Tech,
|
||||
areaid.ww{81:13},areaid Waffle Window,areaid.waf,Used to prevent waffle shifting. When larger than areaid:sl re-defines the placement of waffles. ,Frame,CLDRC
|
||||
areaid.dn{81:50},areaid dead Zon,areaid.dea,“deadzone” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks,Tech,
|
||||
areaid.cr{81:51},areaid critCorner,areaid.cri*,For portions of layout that are not to be put in the critical side do to stress constraints. Should be used sparingly and only over the portion of the layout to remove DRC violations. Avoid using a blanket polygon over the entire layout. This layer is to be used instead of using the noCritSideReg verification option in Stress.\n“critical corner” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks,Tech,Stress
|
||||
areaid.cd{81:52},areaid critSid,areaid.cri*,“criticalsid” area in the DieSealR pcell (Seal Ring) for metal stress relief rule checks,Tech,Stress
|
||||
areaid.ce{81:2},areaid core,areaid.cor,Memory core (memory cells and approved on-pitch only),Tech,DRC
|
||||
areaid.fe{81:3},areaid frame,areaid.fra*,Pads in the frame,Frame,DRC
|
||||
areaid.ed{81:19},areaid ESD,areaid.esd,ESD devices- Surrounds any diffusion or ESD nwell tap connected to a signal pad. (only over ESD devices with special poly/tap exemption rules per LFL),"ESD, Des",DRC
|
||||
areaid.dt{81:11},areaid die cut,areaid.die,"Location of the die within the frame used in frame builder \ngeneration to create blanking for die and other drop-ins. Also used in cldrc/drc for rules in frame to die edge (waffles, nsm, metals etc)",Frame,Tech
|
||||
areaid.mt{81:10},areaid module cut,areaid.mod,Location of e-test modules within the frame used in frame builder generation to create data in scribe lane(example: opaque/clear masks) and to mark location of cells (etest and fab)for frame reports. Also used in drc/cldrc for rules to cell edge.,Frame,Tech
|
||||
areaid.ft{81:12},areaid frameRect,areaid.fra*,Boundary of the frame used in frame builder generation to mark boundary of frame. Also used in cldrc/drc for rules to frame edge ,Frame,DRC/CLDRC
|
||||
areaid.de{81:23},areaid Diode,areaid.dio,The area occupied by diodes; Used to identify diodes during LVS,All,LVS
|
||||
areaid.sc{81:4},areaid standardc,areaid.sta,Cells in the standard cell library (over standard cell IP blocks only) .,Standard cell,DRC
|
||||
areaid.st{81:53},areaid SubstrateCut,areaid.sub,"Regions to be considered as isolated substrates (only to designate 2 different resistively connected substrate \nregions, >100um apart)","Tech, Des, ESD","Latch up, LVS, soft"
|
||||
areaid.en{81:57},areaid extended drain,areaid.ext,Used to identify the extended drain devices ,"Tech, Des, ESD",LVS
|
||||
areaid.le{81:60},areaid LV Native,areaid.lvn,Used to identify the 3V Native NMOS versus 5V Native NMOS,"Tech, Des",LVS
|
||||
areaid.po{81:81},areaid photo ,areaid.pho,The areaid id is to identify the dnwell photo diode,"Tech, Des",DRC
|
||||
areaid.et{81:101},areaid etest,areaid.ete,Used in etest modules,Frame,DRC
|
||||
areaid.ld{81:14},areaid low tap density,areaid.low,"6um tap to diff rule will not be checked in this region\nDiffusion >6u from related tap, requiring >50u from sigPadDiff && sigPadMetNtr).\nShould be used sparingly and only over the portion of the layout to remove DRC violations. This layer is not to be used if a tapping solution can be found. This layer can only be used if there is low risk for latchup. This layer will be reviewed during PDQC.",All,DRC
|
||||
areaid.ns{81:15),areaid not-crtical side,areaid .not,"critSideReg stress rules will not be checked in this region\nCannot be placed in the critical side – uncommon, or where stress \nerrors can't be fixed)",All,DRC
|
||||
areaid.ij{81:17},areaid injection,areaid.inj,Identify all circuits that are susceptible to injection and ensure no signal-pad connected diffusion is within 100u.\n“areaid.inj” encloses any circuitry deemed sensitive (by design team) to injected substrate areaid.inj encloses any PVT compliant circuitry,All,DRC
|
||||
areaid.hl{81:63},areaid.hvnwell,areaid.hvn,"Identify nwell hooked to HV but containing FETs with thin oxide; \nPotential difference across the FET terminals is LV\nUsed over lv devices, operating in lv mode, placed in hv nwells, and should NOT have hvi",All,DRC
|
||||
areaid.re{81:125},areaid rf diode,areaid.rfd,Defines rf diodes that need to be extracted with series resistance (memo GCZ-124/125),All,LVS
|
||||
areaid.rd{81:24},areaid.rdlprobepad,areaid.rdl,Ignore RDL keepouts when opening up PMM2 ,All,CLDRC
|
||||
areaid.sf{81:6},areaid sigPadDiff,,Identify all srdrn diffusions and tap which are intended to be \nconnected to signal pad (io Nets). Goes over diffusions connected to a signal pad - including through a poly resistor,All,LATCHUP
|
||||
areaid.sl{81:7},areaid.sigPadWell,,"Identify all nwells and pwells which are intended to be connected to signal pad (io Nets). Goes over wells with tap connected to a signal pad, including through a poly resistor",All,LATCHUP
|
||||
areaid.sr{81:8},areaid sigPadMetNtr,,"Identify all srcdrn, tap, and wells which are intended to be \nmetallically connected to signal pad (io Nets) not through a resistor. \nMust be used in unison with areaid.sigPadDifff or areaid.sigPadWell.\nUsed with one of the above 2 areaids, nodes metallically \nconnection to a sigPad (not through res)",All,LATCHUP
|
||||
inductor:dg{82:24},ID layer for inductor,,Inductors,"Tech, Des",DRC
|
||||
"t1,2,3 {82:26, 27, 28}",terminal labels for inductor,,Labels required by inductor terminals to be recognized as device,"Tech, Des",LVS
|
||||
poly:ml {66:83},poly device model,,Model name extraction,"Tech, Des, ESD",LVS
|
||||
ncm {92:44},N-Core Implant,,Ncm.dg is available as a drawn layer,All,DRC/CLDRC
|
||||
protect),VPP capacitor,,"Interdigitated, vertical Li1, M1 and M2 capacitor ",All,LVS
|
||||
capm_2t.dg,MIM caps (2 terminal model),,ID layer for MIMCAP that will be treated as 2T device,All,DRC/LVS
|
||||
cpmm:dg{91},Drawn compatible polyimide layer,,Drawn compatible layer and used only inside S8 RF pad,Frame,
|
||||
li1.be{67:10},li1 blockage layer,,Li1 blockage layer used for IP integration (per CWR 137),All,DRC
|
||||
met1.be{68:10},Metal1 blockage layer,,Metal 1 blockage layer used for IP integration (per CWR 137),All,DRC
|
||||
met2.be{69:10},Metal2 blockage layer,,Metal 2 blockage layer used for IP integration (per CWR 137),All,DRC
|
||||
met3.be{70:10},Metal3 blockage layer,,Metal 3 blockage layer used for IP integration (per CWR 137),All,DRC
|
||||
met4.be{71:10},Metal4 blockage layer,,Metal 4 blockage layer used for IP integration (per CWR 137),All,DRC
|
||||
met5.be{72:10},Metal5 blockage layer,,Metal 5 blockage layer used for IP integration (per CWR 137),All,DRC
|
||||
vhvi {74:21},Very High voltage id layer,,Used to identify nodes that operate at 12V nominal (16V max),Des,VHV Rules
|
||||
uhvi {74:22},Ultra High voltage id layer,,Used to identify nodes that operate at 20V nominal,Des,UHV Rules
|
||||
areaid.e0{81:58},Area extended drain,areaid.ext,Used to identify 20V drain extended devices,Des,LVS
|
||||
areaid.zr{81:18},Area zener diode,areaid.zen,Used to identify Zener diodes,Des,LVS
|
||||
fom.dy{},FOM dummy,,FOM waffle drawn in this layer,All,Waffles
|
||||
prune:dg{84:44},prune,,Areas ignored by LVS ,Frame,LVS
|
||||
areaid:cr {81:55},copper pillar (.cuPillar),areaid.cup,"Placement of Cu pillar over the pad area, streamed out to Amkor, s8pfhd-10r flow only",Die,CLDRC s8pfhd-10r
|
||||
cyprotect.dg {56.44},External F25 layer,cyprotect.dg,Switch to direct streaming to drawn (no protect) or mask layer (with protect),Frame,CLDRC
|
||||
cytextmc.dg {50:44},Locations for mask compose,cytextmc.dg,Text to extract placement for Fab25 tool,Frame,CLDRC
|
||||
cypsbr.dg {51:44},No phaseshift allowed,cypsbr.dg,Phaseshift layer common to all F25 phaseshift masks,Frame,
|
||||
areaid:ag{81:79},analog,areaid.ana,Used to identify analog circuits,All,Analog
|
||||
natfet.dg {124:21},DEFETs,natfet.dg,"Add TUNM for SONOS channel implants. See SPR 117559, SGL-529",All,DRC/CLDRC
|
||||
areaid:lw,Ultra High voltage id layer, ,Areaid low voltage: UHV box to put all HV/LV curcuits in,All,Analog
|
||||
"* To distinguish the layers, the full name of the layer needs to be turned on in the LSW window",,,,,
|
||||
"As the layers are displayed in LSW window in icfb version 5.0; For purpose layer displayed in version 5.1, pls refer table C3"
|
||||
|
Can't render this file because it has a wrong number of fields in line 82.
|
|
|
@ -0,0 +1,28 @@
|
|||
Explanation of symbols:
|
||||
* ``-`` = Layer illegal for the device
|
||||
* ``+`` = Layer allowed to overlap
|
||||
* ``D`` = DRAWN indicates that a layer is drawn by Design.
|
||||
* ``C`` = CREATED indicates that the layer is only created by CAD.
|
||||
|
||||
.. rubric:: Footnotes
|
||||
|
||||
.. [#f1] Low vt needs to be set on the schematic element
|
||||
.. [#f2] Ncm is drawn inside core. Otherwise it is created in periphery. See rules ncm.X.* for details
|
||||
.. [#f3] Drawn over half of device
|
||||
.. [#f4] ASSUMPTION: FET models will be same regardless of backend flow
|
||||
.. [#f5] The 2 core FETs and flash npass must have a poly.ml label with their model name.
|
||||
.. [#f6] over the drain
|
||||
.. [#f7] over the source
|
||||
.. [#f8] Information for RCX
|
||||
.. [#f9] Uses a black box for LVS. This is a fixed layout; Use symbol provided by modeling group
|
||||
.. [#f10] LVS will check that phighvt inside areaid.ce overlaps ncm
|
||||
.. [#f11] The default model is sonos_e, sonos_de and nvssonos_e. If sonos_p, sonos_dp and nvssonos_p model are required, poly.ml must be used
|
||||
.. [#f12] The capacitor.dg is drawn 0.17um from the edge of the cell to be LVS clean
|
||||
.. [#f13] Devices are LVS'ed by cell name, m=1 per cell, fixed area and perimeter (see QHC-18)
|
||||
.. [#f14] (dnwell not (pwres or pnp or npn or areaid.en or areaid.de or areaid.po)) not nwell must have condiode text; Refer to VUN-104, 192 for condiode usage
|
||||
.. [#f15] Tech element is created by the user, no CAD supplied tech element
|
||||
.. [#f16] There are multiple configurations of the Cu inductor. The layers present in one configuration may not be drawn in the other configuration. Also rdl will not be routed over met5 cu inductor, not checkable by CAD flow.
|
||||
.. [#f17] Used for substrate noise isolation regions only
|
||||
.. [#f18] Either UHVI or areaid.low_vt should be drawn over the sturctures
|
||||
.. [#f19] Psub-Deep Nwell Diode must have condiode text "condiodeHvPsub"; CVA-596
|
||||
.. [#f20] mrp1 can't overlay capacitor.dg: exempted s8rf2_xcmvpp11p5x11p7_lim5shield from the rule
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import csv
|
||||
import os
|
||||
import pprint
|
||||
import sys
|
||||
|
||||
__dir__ = os.path.dirname(os.path.abspath(__file__))
|
||||
|
||||
TSV_FILE = os.path.join(__dir__, "table-f2a-lvs.tsv")
|
||||
|
||||
|
||||
def main(arg):
|
||||
rows = []
|
||||
with open(TSV_FILE, newline='') as csvfile:
|
||||
reader = csv.reader(csvfile, delimiter='\t')
|
||||
for r in reader:
|
||||
rows.append(list(c.strip() for c in r))
|
||||
|
||||
rowlen = max(len(r) for r in rows)
|
||||
for r in rows:
|
||||
while len(r) < rowlen:
|
||||
r.append('')
|
||||
|
||||
clen = [0] * rowlen
|
||||
for i, _ in enumerate(clen):
|
||||
clen[i] = max(len(r[i]) for r in rows)
|
||||
|
||||
for r in rows:
|
||||
for i, m in enumerate(clen):
|
||||
r[i] = r[i].ljust(m)
|
||||
|
||||
rows.insert(1, ['-'*m for m in clen])
|
||||
|
||||
for r in rows:
|
||||
print("|", " | ".join(r), "|")
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main(sys.argv))
|
||||
|
|
@ -0,0 +1,91 @@
|
|||
Category Name Used? Required schematic elements diff.dg diff.rs diff.ct cfom.wp tap.dg dnwell:dg pwbm.dg pwdem:dg hvtr.dg nwell.dg hvtp:dg lvtn:dg pwell.rs pwell.ct ncm.dg [#f2]_ tunm:dg hvi:dg rpm:dg poly.dg poly.rs poly.ct poly:ml ldntm:dg npc:dg nsdm.dg psdm.dg licon.dg li1.dg li.rs li.ct capm:dg capm_2t.dg metX.dg metX.fe met1:dg met2:dg met3:dg met4.dg met5.dg rdl.dg inductor:dg capacitor.dg areaid.le areaid.en pnp.dg npn.dg areaid.st areaid.de areaid.re areaid.po areaid:ce areaid.ed areaid.ext UHVI areaid.low_vt Drawn Route / Comments Layout Model
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RESISTOR n diff resistor X res resn D D D + - + - + - - - - + + - + - + - - - + + + D - + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdn
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RESISTOR HV n diff resistor X res resnhv D D D + - + - + - - - - + + - + D + - - - + + + D - + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdn_hv
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RESISTOR p diff resistor X res resp D D D + - + - + - D - - + + C + - + - - - + + + - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdp
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RESISTOR p diff resistor NV res resp D D D + - + - + - D - - + + C + - + - - - + + + - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdp
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RESISTOR HV p diff resistor X res resphv D D D + - + - + - D - - + + - + D + - - - + + + - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - mrdp_hv
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RESISTOR Isolated Pwell resistor X respw + + + + D D - - - - + + D D + + + + - - - + + + + + + + + + + + + + + + + + + + - - - + + + + + - - + - - xpwres
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RESISTOR n+ poly resistor X res - - - + - + - + - + - - + + - + + - D D D + + - + + + + + - + + + - + + + + + + + - [#f20]_ - - - - + - + - - + - - mrp1
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RESISTOR p+ poly resistor X res3 - - - + - + - + - + - - + + + + + D D D D + + D - D + + + - + + + - + + + + + + + - - - - - + - + - - + - - xhrpoly_*
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RESISTOR li resistor X res + + + + + + - + - + + + + + + + + + + + + + + + + + - D D D + + + + + + + + + + + - - - + + + + + - - + - - mrl1
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RESISTOR metal fuse X mrmX - - - + - + - + - - - - + + - - - - - + + + + + - - - - + + D D + + + + + + - - - - - - + - + - - - - - metX AND metX.fe mrmX
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32 A CMOS nmos 1.8V X nfet D - - + - + - - - - - - + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - + + - - nshort
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32 A CMOS pmos 1.8V X pfet D - - + - + - - - D C - + + C - - - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - - + - - pshort
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32 A CMOS Low Vt pmos 1.8V 32A X pfet D - - + - + - - - D - D + + - - - - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - - - - - plowvt
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32 A CMOS High Vt pmos 1.8V 32A [#f10]_ X pfet D - - + - + - - - D D C + + + - - - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - + - - - phighvt
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32 A CMOS Low Vt nmos 1.8V 32A X nfet D - - + - + - - - - - D + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - - - - nlowvt
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32 A CMOS nmos_core [#f5]_ X nfet D - - + - + - - - - - - + + - - - - D - - D - - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - npass npd
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32 A CMOS nmos_core NV [#f5]_ nfet D - - + - + - - - - - - + + D - - - D - - D D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - npassll npdll
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32 A CMOS pmos_core [#f5]_ X pfet D - - + - + - - - D D C + + D - - - D - - D - - - D + + - - + + + - + + + + + + + - - - - - + - + - D - - - ppu
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32 A CMOS pmos_core NV [#f5]_ pfet D - - + - + - - - D D C + + - - - - D - - D - - - D + + - - + + + - + + + + + + + - - - - - + - + - D - - - ppull
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32 A CMOS Low Vt nmos_core [#f5]_ X nfet D - - + - + - - - - - D + + - - - - D - - D - - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - nlvtpass
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32 A CMOS Low Vt Varactor X capbn_b - - - + D + - - - D - C + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - - - - xcnwvc
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32 A CMOS High Vt Varactor X capbn_b - - - + D + - - - D D C + + C - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - - - - xcnwvc2
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32 A CMOS HV varactor (floating gate) X capbn_b - - - + D + - - - D - D + + - - D - D - - + - - D - - + - - + + + - + + + + + + + - - - - - + - + - - - - - xchvnwc
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SONOS (& SONOS Latch) SONOS fet [#f11]_ X nfet D - - + - D - - - - - D + + - D - - D - - + D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - sonos_p/e
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SONOS (& SONOS Latch) SONOS fet [#f11]_ nfet D - - + - D - - - - - D + + - D - - D - - + D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - sonos_de/dp
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SONOS (& SONOS Latch) NV SONOS fet [#f11]_ nfet D - - + - + - - - - - D + + - D - - D - - D D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - nvssonos_p/e
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110A CMOS HV nmos 5/10.5V X nfet D - - + - + - - - - - - + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - + - - nhv
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110A CMOS HV nmos 5/10.5V nfet D - - + - + - - - - - - + + - - D - D - - D - - D - + + - - + + + - + + + + + + + - - - - - + - + - - + - - nhvcore
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110A CMOS HV pmos 5/10.5V X pfet D - - + - + - - - D - - + + - - D - D - - + - - - D + + - - + + + - + + + + + + + + - - - - + - + - - + - - phv
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110A CMOS HV pmos 5/10.5V pfet D - - + - + - - - D - - + + - - D - D - - D - - - D + + - - + + + - + + + + + + + - - - - - + - + - - + - - phvcore
|
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110A CMOS Native nmos 5V X nfet D - - + - + - - - - - D + + - - D - D - - + - - D - + + - - + + + - + + + + + + + + - - - - + - + - - - - - nhvnative
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110A CMOS Native nmos 3V X nfet D - - + - + - - - - - D + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - D - - - + - + - - - - - ntvnative
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110A CMOS Flash npass [#f5]_ X nfet D - - + - + - - - - - - + + - - D - D - - D D - D - + + - - + + + - + + + + + + + - - - - - + - + - D - - - fnpass
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110A CMOS Flash npass NV nfet D - - + - + - - - - - - + + - - D - D - - D D - D [#f3]_ - + + - - + + + - + + + + + + + - - - - - + - + - D - - - nvsrnpass
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110A CMOS VHV nmos 5/16V DE X nfetextd D [#f7]_ - - + D [#f6]_ - - - - D - - + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - D - - + - + - - - - - nvhv
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110A CMOS VHV pmos 5/16V DE X pfetextd D [#f7]_ - - + D [#f6]_ D - - - D [#f3]_ - - + + - - D - D - - + - - - D + + - - + + + - + + + + + + + - - D - - + - + - - - - - pvhv
|
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110A CMOS UHV nmos 5/20V DE nfetextd D [#f7]_ - - + D [#f6]_ D [#f3]_ D [#f3]_ - - D [#f3]_ - D [#f3]_ + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20vhv1
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110A CMOS UHV iso nmos 5/20V DE nfetextdiso D [#f7]_ - - + D [#f6]_ D [#f3]_ D [#f3]_ - - D [#f3]_ - D [#f3]_ + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20vhviso1
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110A CMOS UHV Native nmos 5/20V DE nfetextd D [#f7]_ - - + D [#f6]_ D [#f3]_ D [#f3]_ - - D [#f3]_ - D + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20nativevhv1
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110A CMOS UHV Zvt nmos 5/20V DE nfetextd D [#f7]_ - - + D [#f6]_ D [#f3]_ D - - D [#f3]_ - D + + - - D - D - - + - - D - + + - - + + + - + + + + - - - - - - + - - - D D D n20zvtvhv1
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110A CMOS UHV pmos 5/20V DE pfetextd D [#f7]_ - - + D [#f6]_ D D [#f3]_ D [#f3]_ - D [#f3]_ - D [#f3]_ + + - - D - D - - + - - - D + + - - + + + - + + + + + + + - - - - - + - - - D D D p20vhv1
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CAPACITOR MiM (3 Terminal) cmim3c - + + + - + - + - + + + + + + + + + - + + + + + + + + - + + D - + - - D + + + + - - - - + + + + + - - + - - xcmimc
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CAPACITOR MiM (2 Terminal) cmimc + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + D D + - + D + + + + - - - - + + + + + - - + - - xcmimc2
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CAPACITOR VPP [#f9]_ X + + + + + + - + - + + + + + + + + + + + + + + + + + - D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp xcmvpp_2
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CAPACITOR VPP over NHVNATIVE X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp2_nhvnative10x4
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CAPACITOR VPP over PHV X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp2_phv5x4
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CAPACITOR VPP and NHVNATIVE X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D + + + + D - - + + + + + - - + - - xcmvppx4_2xnhvnative10x4
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CAPACITOR 4-Terminal VPP (with Met3 shield) [#f12]_ X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D + + + + D - - + + + + + - - + - - xcmvpp1p8x1p8_m3shield xcmvpp8p6x7p9_m3shield xcmvpp4p4x4p6_m3shield xcmvpp11p5x11p7_m3shield
|
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CAPACITOR 4-terminal VPP (with M5 shield) [#f12]_ X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D D D + + D - - + + + + + - - + - - xcmvpp11p5x11p7_m5shield xcmvpp11p5x11p7_polym5shield xcmvpp11p5x11p7_lim5shield xcmvpp8p6x7p9_m3_lim5shield xcmvpp11p5x11p7_m3_lim5shield xcmvpp4p4x4p6_m3_lim5shield xcmvpp11p5x11p7_m1m4m5shield xcmvpp11p5x11p7_polym50p4shield
|
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CAPACITOR 4-terminal VPP (with M4 shield) [#f12]_ X vppcap + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D D + + + D - - + + + + + - - + - - xcmvpp11p5x11p7_m4shield xcmvpp11p5x11p7_polym4shield xcmvpp6p8x6p1_polym4shield xcmvpp6p8x6p1_lim4shield
|
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CAPACITOR 3-Terminal VPP [#f12]_ X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D + + + + + D - - + + + + + - - + - - xcmvpp1p8x1p8 xcmvpp3 xcmvpp4 xcmvpp5 xcmvpp4p4x4p6_m1m2 xcmvpp11p5x11p7_m1m2
|
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CAPACITOR 3-Terminal VPP [#f12]_ (for S8Q/S8P ONLY) X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D + + + + D - - + + + + + - - + - - xcmvpp8p6x7p9_m3_lishield xcmvpp4p4x4p6_m3_lishield xcmvpp11p5x11p7_m3_lishield
|
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CAPACITOR 3-Terminal VPP [#f12]_ (for S8P ONLY) X cap_int3 + + + + + + - + - + + + + + + + + + + + + + + + + + + D + + - + + - D D D D + + + D - - + + + + + - - + - - xcmvpp11p5xx11p7_m1m4 xcmvpp_hd5_*
|
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INDUCTOR Inductor inductor + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + D + + + D - - - + + + + + - - + - - xind
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INDUCTOR Cu Inductor X ind4 + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + D + D [#f16]_ D [#f16]_ D D [#f16]_ D - - - - - - - - - - - - - *xind4*
|
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INDUCTOR Balun Inductor [#f15]_ X + + + + + + - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + D D D D - - - - - - - - - - - - - *balun*
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DIODE nDiode X lvsdiode D - - + - + - + - - - - + + - + - + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - + + - - ndiode
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DIODE HV nDiode X lvsdiode D - - + - + - + - - - - + + - + D + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - - + - - ndiode_h
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DIODE RF ESD HV nDiode [#f13]_ X lvsdiode D - - + - - - + - - - - + + - + D + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - - D - - xesd_ndiode_h_X (where X=100 200 300)
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DIODE RF ESD HV Deep Nwell nDiode [#f13]_ X lvsdiode D - - + - D - + - - - - + + - + D + - - - + + + D - + + - - + + + - + + + + + + + - - - - - + D + - - D - - xesd_ndiode_h_dnwl_X (where X=100 200 300)
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DIODE pDiode X lvsdiode D - - + - + - + - D - - + + C + - + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - + - - pdiode
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DIODE pDiode NV lvsdiode D - - + - + - + - D - - + + C + - + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - + - - pdiode
|
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DIODE HV pDiode X lvsdiode D - - + - + - + - D - - + + - + D + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - - + - - pdiode_h
|
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DIODE RF ESD HV pDiode [#f13]_ X lvsdiode D - - + - + - + - D - - + + - + D + - - - + + + - D + + - - + + + - + + + + + + + - - - - - + D + - - D - - xesd_pdiode_h_X (where X=100 200 300)
|
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DIODE Photo Diode X lvsdiode - - - + D D - - - D - - - - - - - - - - - - - - D - + + - - + + + - + + + + + + + - - - - - + D + D - - - - dnwdiode_psub
|
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DIODE Low Vt pdiode [#f8]_ X diode D + + + + + - + - D - D + + + + + + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + - + + - - pdiode_lvt
|
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DIODE High Vt pDiode [#f8]_ X diode D + + + + + - + - D D C + + + + - + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + - + + - - pdiode_hvt
|
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DIODE High Vt pDiode NV [#f8]_ diode D + + + + + - + - D D C + + C + - + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + - + + - - pdiode_hvt
|
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DIODE Low Vt nDiode [#f8]_ X diode D + + + + + - + - + + D + + + + + + + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + + - + + - - ndiode_lvt
|
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DIODE NV SONOS Diode [#f8]_ diode D + + + + + - + - + + D + + + D + + + + + + D + + + + + + + + + + + + + + + + + + + + + + + + + + - D + - - ndiode_nvs
|
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DIODE Native nDiode [#f8]_ X diode D + + + + + - + - + + D + + + + D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - ndiode_native
|
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DIODE Nwell Diode [#f8]_ X diode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - nwdiode
|
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DIODE Nwdiode_victim [#f17]_ X lvsdiode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - nwdiode
|
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DIODE Nwdiode_aggressor [#f17]_ X lvsdiode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - nwdiode
|
||||
DIODE RF Nwell Diode [#f8]_ X diode + + + + + - - + - D + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D - + + - - xnwdiode_rf
|
||||
DIODE Pwell-Deep Nwell Diode [#f8]_ X diode + + + + + D - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - - + + - - dnwdiode_pw
|
||||
DIODE RF ESD Pwell-Deep Nwell Diode [#f8]_ X lvsdiode + + + + + D - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D + - + D - - xesd_dnwdiode_pw_X (where X=100 200 300)
|
||||
DIODE RF Pwell-Deep Nwell Diode [#f8]_ X diode + + + + + D - + - - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + D - + + - - xdnwdiode_pwell_rf
|
||||
DIODE Psub-Deep Nwell Diode [#f8]_ X diode + + + + + D - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_psub
|
||||
DIODE Psub-Deep Nwell Diode [#f17]_ X lvsdiode + + + + + D - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_psub
|
||||
DIODE Psub-Deep Nwell Diode [#f17]_ X lvsdiode + + + + + D - + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_psub
|
||||
DIODE Psub-Deep Nwell Diode [#f8]_ [#f19]_ diode + + + + + D D + - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + D [#f18]_ D [#f18]_ dnwhvdiode_psub
|
||||
DIODE HV Pwell-Deep Nwell Diode [#f8]_ [#f19]_ diode + + + + + D - D - + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + - + + - - dnwdiode_hvpw
|
||||
PNP Parasitic PNP X pnp4 D - - + D - - - - D + - + + - + - + - - - + + + D D + + - - + + + - + + + + + + + - - - D - + - + - - - - - Layout provided by technology pnppar pnppar5x
|
||||
PNP Parasitic HV Gated NPN X npn4 D - - + + D - - - D + - - - - + D + D - - + + + D D + + - - + + + - + + + + + + + - - - - D + - + - - - - - Layout provided by technology npn_1x1_2p0_hv
|
||||
PNP Parasitic NPN X npn4 D - - + + D - - - D + - - - - + - + - - - + + + D D + + - - + + + - + + + + + + + - - - - D + - + - - - - - Layout provided by technology npnpar1x1 npnpar1x2
|
||||
ESD transistor LV nESD transistor X nfet D - - + - + - - - - - - + + - - - - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - D - - NMOS with ESD_nwell_tap nshortesd
|
||||
ESD transistor HV nESD transistor X nfet D - - + - + - - - - - - + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - D - - NMOS with ESD_nwell_tap nhvesd
|
||||
ESD transistor HV Native nESD transistor X nfet D - - + - + - - - - - D + + - - D - D - - + - - D - + + - - + + + - + + + + + + + - - - - - + - + - - D - - NMOS with ESD_nwell_tap nhvnativeesd
|
||||
ESD transistor HV pESD transistor X pfet D - - + - + - - - D - - + + - - D - D - - + - - - D + + - - + + + - + + + + + + + - - - - - + - + - - D - - phvesd
|
||||
|
|
|
@ -0,0 +1,9 @@
|
|||
Explanation of symbols:
|
||||
* ``-`` = Layer not created for the device
|
||||
* ``+`` = Layer allowed to overlap
|
||||
* ``C`` = CREATED
|
||||
* ``nr`` = next revision
|
||||
|
||||
.. rubric:: Footnotes
|
||||
|
||||
.. [#fb1] For RCX information
|
||||
|
|
@ -0,0 +1,42 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import csv
|
||||
import os
|
||||
import pprint
|
||||
import sys
|
||||
|
||||
__dir__ = os.path.dirname(os.path.abspath(__file__))
|
||||
|
||||
TSV_FILE = os.path.join(__dir__, "table-f2b-mask.tsv")
|
||||
|
||||
|
||||
def main(arg):
|
||||
rows = []
|
||||
with open(TSV_FILE, newline='') as csvfile:
|
||||
reader = csv.reader(csvfile, delimiter='\t')
|
||||
for r in reader:
|
||||
rows.append(list(c.strip() for c in r))
|
||||
|
||||
rowlen = max(len(r) for r in rows)
|
||||
for r in rows:
|
||||
while len(r) < rowlen:
|
||||
r.append('')
|
||||
|
||||
clen = [0] * rowlen
|
||||
for i, _ in enumerate(clen):
|
||||
clen[i] = max(len(r[i]) for r in rows)
|
||||
|
||||
for r in rows:
|
||||
for i, m in enumerate(clen):
|
||||
r[i] = r[i].ljust(m)
|
||||
|
||||
rows.insert(1, ['-'*m for m in clen])
|
||||
|
||||
for r in rows:
|
||||
print("|", " | ".join(r), "|")
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main(sys.argv))
|
||||
|
|
@ -0,0 +1,81 @@
|
|||
Category Name Used? Layout Model and required schematic element FOM DNM PWBM PWDEM NWM HVTPM LVTNM NCM TUNM ONOM LVOM RPM P1M HVNTM NTM LDNTM NPC NSDM PSDM LICM1 LI1M CAPM MM1 MM2 MM3 MM5 CU1M INDM Drawn Route / Comments
|
||||
RESISTOR n diff resistor res r sky130_fd_pr__res_generic_nd C + - - - - - - - - - + - - - - - C - + + + + + + + + +
|
||||
RESISTOR HV n diff resistor res r mrdn_hv C + - - - - - - - - C + - C C - - C - + + + + + + + + +
|
||||
RESISTOR p diff resistor res r sky130_fd_pr__res_generic_pd C + - - C C - C - - - + - - C - - - C + + + + + + + + +
|
||||
RESISTOR p diff resistor NV res r sky130_fd_pr__res_generic_pd C + - - C C - C - - - + - - C - - - C + + + + + + + + +
|
||||
RESISTOR HV p diff resistor res r mrdp_hv C + - - C - - - - - C + - - C - - - C + + + + + + + + +
|
||||
RESISTOR Isolated Pwell resistor respw sky130_fd_pr__res_iso_pw C C - - - + + + + + + + - + + + + + + + + + + + + + + +
|
||||
RESISTOR n+ poly resistor res sky130_fd_pr__res_generic_po - + - - + - - - + + + - C + + + - + + + + + + + + + + +
|
||||
RESISTOR p+ poly resistor res3 xhrpoly_*_* - + - - + - - + + + + C C - C - C - C + + + + + + + + +
|
||||
RESISTOR li resistor res sky130_fd_pr__res_generic_l1 + + - - + + + + + + + + + + + + + + + - C + + + + + + +
|
||||
RESISTOR metal fuse_D mrmX mrmX - + - - - - - - - - - + - - - + + + + - - + + + C + + + metX AND metX.fe
|
||||
RESISTOR metal fuse_T mrmX mrmX - + - - - - - - - - - + - - - + + + + - - + + C + + + + metX AND metX.fe
|
||||
32 A CMOS nmos 1.8V nfet sky130_fd_pr__nfet_01v8 C + - - - - - - - - - - C - - - - C - + + + + + + + + +
|
||||
32 A CMOS pmos 1.8V pfet sky130_fd_pr__pfet_01v8 C + - - C C - C - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS pmos 1.8V NV pfet sky130_fd_pr__pfet_01v8 C + - - C C - C - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS Low Vt pmos 1.8V 32A pfet sky130_fd_pr__pfet_01v8_lvt C + - - C - C - - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS High Vt pmos 1.8V 32A pfet sky130_fd_pr__pfet_01v8_hvt C + - - C C C C - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS High Vt pmos 1.8V 32A NV pfet sky130_fd_pr__pfet_01v8_hvt C + - - C C C C - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS Low Vt nmos 1.8V 32A nfet sky130_fd_pr__nfet_01v8_lvt C + - - - - C - - - - - C - - - - C - + + + + + + + + +
|
||||
32 A CMOS nmos_core nfet sky130_fd_pr__special_nfet_pass C + - - - - - - - - - - C - - - - C - + + + + + + + + +
|
||||
32 A CMOS nmos_core nfet sky130_fd_pr__special_nfet_latch C + - - - - - - - - - - C - - - - C - + + + + + + + + +
|
||||
32 A CMOS nmos_core NV nfet sky130_fd_pr__special_nfet_pass_lowleakage C + - - - - - C - - - - C - - C - C - + + + + + + + + +
|
||||
32 A CMOS nmos_core NV nfet sky130_fd_pr__special_nfet_latch_lowleakage C + - - - - - C - - - - C - - C - C - + + + + + + + + +
|
||||
32 A CMOS pmos_core pfet sky130_fd_pr__special_pfet_pass C + - - C C C C - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS pmos_core NV pfet sky130_fd_pr__special_pfet_pass_lowleakage C + - - C C C - - - - - C - C - - - C + + + + + + + + +
|
||||
32 A CMOS Low Vt nmos_core C + - - - - C - - - - - C - - - - C - + + + + + + + + +
|
||||
32 A CMOS Low Vt Varactor capbn sky130_fd_pr__cap_var_lvt C + - - C - C - - - - - C - C - - C - + + + + + + + + +
|
||||
32 A CMOS High Vt Varactor capbn sky130_fd_pr__cap_var_hvt C + - - C C C C - - - - C - C - - C - + + + + + + + + +
|
||||
32 A CMOS HV varactor (floating gate) C C - - C - C - - - C - C C C - - C - - + + + + + + + +
|
||||
SONOS (& SONOS Latch) SONOS fet nfet sky130_fd_bs_flash__special_sonosfet_original C C - - - - C - C C C - C - C C - C - + + + + + + + + +
|
||||
SONOS (& SONOS Latch) SONOS fet nfet sky130_fd_bs_flash__special_sonosfet_star C C - - - - C - C C C - C - C C - C - + + + + + + + + +
|
||||
SONOS (& SONOS Latch) NV SONOS fet nfet nvssonos_p C + - - - - C - C C C - C - C C - C - + + + + + + + + +
|
||||
SONOS (& SONOS Latch) NV SONOS fet nfet nvssonos_e C + - - - - C - C C C - C - C C - C - + + + + + + + + +
|
||||
110A CMOS HV nmos 5/10.5V nfet sky130_fd_pr__nfet_g5v0d10v5 C + - - - - - - - - C - C C C - - C - + + + + + + + + +
|
||||
110A CMOS HV pmos 5/10.5 V pfet sky130_fd_pr__pfet_g5v0d10v5 C + - - C - - - - - C - C - C - - - C + + + + + + + + +
|
||||
110A CMOS Native nmos 5V nfet sky130_fd_pr__nfet_05v0_nvt C + - - - - C - - - C - C C C - - C - + + + + + + + + +
|
||||
110A CMOS Native nmos 3V nfet sky130_fd_pr__nfet_03v3_nvt C + - - - - C - - - C - C C C - - C - + + + + + + + + +
|
||||
110A CMOS Flash npass nfet sky130_fd_pr__special_nfet_pass_flash C + - - - - - - - - C - C - C C - C - + + + + + + + + +
|
||||
110A CMOS Flash npass NV nfet nvsrnpass C + - - - - - - - - C - C - C C - C - + + + + + + + + +
|
||||
110A CMOS VHV nmos 5/16V DE nfet sky130_fd_pr__nfet_g5v0d16v0 C - - - C - - - - - C - C C C - - C - + + + + + + + + +
|
||||
110A CMOS VHV pmos 5/16V DE pfet sky130_fd_pr__pfet_g5v0d16v0 C C - - C - - - - - C - C - C - - - C + + + + + + + + +
|
||||
110A CMOS UHV nmos 5/20V DE nfete C C C - C - C - - - C - C - - - - C - + + + + + + + + +
|
||||
110A CMOS UHV iso nmos 5/20V DE nfete C C C - C - C - - - C - C - - - - C - + + + + + + + + +
|
||||
110A CMOS UHV Native nmos 5/20V DE TBA C C C - C - C - - - C - C - - - - C - + + + + + + + + +
|
||||
110A CMOS UHV Native iso nmos 5/20V DE nfete C C C - C - C - - - C - C - - - - C - + + + + + + + + +
|
||||
110A CMOS UHV pmos 5/20V DE pfete C C C C C - C - - - C - C - - - - - C + + + + + + + + +
|
||||
CAPACITOR MiM cmim3 sky130_fd_pr__model__cap_mim + + - - + + + + + + + + + + + + + + + + + C + C + + + +
|
||||
CAPACITOR VPP cap sky130_fd_pr__cap_vpp_XXXXXX + + - - + + + + + + + + + + + + + + + - C - C C + + + -
|
||||
CAPACITOR VPP (with met3 shield) vppca + + - - + + + + + + + + + + + + + + + - C - C C C + + -
|
||||
INDUCTOR Inductor induc sky130_fd_pr__ind + + - - + + + + + + + + + + + + + + + + + + + + + + + C
|
||||
INDUCTOR Cu Inductor induc sky130_fd_pr__ind + + - - + + + + + + + + + + + + + + + + + + + + + C C -
|
||||
INDUCTOR Balun Inductor induc sky130_fd_pr__ind + + - - + + + + + + + + + + + + + + + + + + + + + C C -
|
||||
DIODE nDiode lvsdi sky130_fd_pr__diode_pw2nd_05v5 C + - - - - - - + + - + - - - + + C - + + + + + + + + +
|
||||
DIODE HV nDiode lvsdi sky130_fd_pr__diode_pw2nd_11v0 C + - - - - - - + + C + - C C + + C - + + + + + + + + +
|
||||
DIODE RF ESD HV nDiode lvsdi sky130_fd_pr__diode_pw2nd_11v0 C - - - - - - - + + C + - C C + + C - + + + + + + + + +
|
||||
DIODE RF ESD Deep Nwell nDiode lvsdi C C - - - - - - + + C + - C C + + C - + + + + + + + + +
|
||||
DIODE pDiode lvsdi sky130_fd_pr__diode_pd2nw_05v5 C + - - C C - C + + - + - - C + + - C + + + + + + + + +
|
||||
DIODE pDiode NV lvsdi sky130_fd_pr__diode_pd2nw_05v5 C + - - C C - C + + - + - - C + + - C + + + + + + + + +
|
||||
DIODE HV pDiode lvsdi sky130_fd_pr__diode_pd2nw_11v0 C + - - C - - - + + C + - - C + + - C + + + + + + + + +
|
||||
DIODE RF ESD HV pDiode lvsdi sky130_fd_pr__diode_pd2nw_11v0 C + - - C - - - + + C + - - C + + - C + + + + + + + + +
|
||||
DIODE Photo Diode lvsdi dnwdiode C C - - C C - C - - - - - - C - - C - + + + + + + + + +
|
||||
DIODE Low Vt pdiode [#fb1]_ diode sky130_fd_pr__diode_pd2nw_05v5_lvt C + - - C - C + + + + + + + C + + - C + + + + + + + + +
|
||||
DIODE High Vt pDiode [#fb1]_ diode sky130_fd_pr__diode_pd2nw_05v5_hvt C + - - C C C C + + + + + + C + + - C + + + + + + + + +
|
||||
DIODE High Vt pDiode NV [#fb1]_ diode sky130_fd_pr__diode_pd2nw_05v5_hvt C + - - C C C C + + + + + + C + + - C + + + + + + + + +
|
||||
DIODE Low Vt nDiode [#fb1]_ diode sky130_fd_pr__diode_pw2nd_05v5_lvt C + - - + + C + + + + + + + - + + C - + + + + + + + + +
|
||||
DIODE NV SONOS Diode [#fb1]_ diode ndiode_nvs C + - - + + C + C C C + + + + C + + + + + + + + + + + +
|
||||
DIODE Native nDiode [#fb1]_ diode sky130_fd_pr__diode_pw2nd_05v5_nvt C + - - + + C + + + C + + C C + + + + + + + + + + + + +
|
||||
DIODE Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_ps2nw + - - - C + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE RF Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_ps2nw + - - - C + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE Pwell-Deep Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_pw2dn + C - - - + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE RF ESD Pwell-Deep Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_pw2dn + C - - - + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE RF Pwell-Deep Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_pw2dn + C - - - + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE Psub-Deep Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_ps2dn + C - - + + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE Psub-Deep Nwell Diode [#fb1]_ diode sky130_fd_pr__model__parasitic__diode_ps2dn + C C - + + + + + + + + + + + + + + + + + + + + + + + +
|
||||
DIODE HV Pwell-Deep Nwell Diode [#fb1]_ diode dnwdiode_hvpw + C - - + + + + + + + + + + + + + + + + + + + + + + + +
|
||||
PNP Parasitic PNP pnp4 sky130_fd_pr__pnp_05v5_W0p68L0p68 C - - - C C - C - - - + - - C - + C C + + + + + + + + + Layout provided by technology
|
||||
PNP Parasitic NPN pnp4 sky130_fd_pr__npn_05v5 C C - - C + - - - - - + - - - - + C C + + + + + + + + + Layout provided by technology
|
||||
ESD transistor LV nESD transistor nfet sky130_fd_pr__esd_nfet_01v8 C + - - - - - - - - - - C - - - - C - + + + + + + + + + NMOS with ESD_nwell_tap
|
||||
ESD transistor HV nESD transistor nfet sky130_fd_pr__esd_nfet_g5v0d10v5 C + - - - - - - - - C - C C C - - C - + + + + + + + + + NMOS with ESD_nwell_tap
|
||||
ESD transistor HV Native nESD transistor C + - - - - C - - - C - C C C - - C - + + + + + + + + +
|
||||
ESD transistor HV pESD transistor pfet sky130_fd_pr__esd_pfet_g5v0d10v5 C + - - C - - - - - C - C - C - - - C + + + + + + + + +
|
||||
|
Can't render this file because it has a wrong number of fields in line 2.
|
|
|
@ -0,0 +1,52 @@
|
|||
Mask,Acronym,Used in SKY130
|
||||
Field Oxide,FOM,X
|
||||
Deep N-Well,DNM,X
|
||||
P-Well Block Mask,PWBM,
|
||||
P-Well Drain Extended ,PWDEM,
|
||||
N-Well*,NWM,X
|
||||
High Vt PCh*,HVTPM,X
|
||||
Low Vt Nch*,LVTNM,X
|
||||
HLow VT PCh Radio*,HVTRM,X
|
||||
N-Core Implant,NCM,
|
||||
Tunnel Mask,TUNM,X
|
||||
ONO Mask,ONOM,X
|
||||
Low Voltage Oxide,LVOM,X
|
||||
Resistor Protect,RPM,X
|
||||
Poly 1,P1M,X
|
||||
N-tip Implant,NTM,X
|
||||
High Volt. N-tip,HVNTM,X
|
||||
Lightly Doped N-tip,LDNTM,X
|
||||
Nitride Poly Cut,NPCM,X
|
||||
P+ Implant,PSDM,X
|
||||
N+ Implant,NSDM,X
|
||||
Local Intr Cont.1,LICM1,X
|
||||
Local Intrcnct 1,LI1M,X
|
||||
Contact,CTM1,X
|
||||
Open Frame Mask,OFM,
|
||||
Metal 1,MM1,X
|
||||
Via,VIM,X
|
||||
Capacitor MiM,CAPM,
|
||||
Metal 2,MM2,X
|
||||
Via 2-TNV,VIM2,
|
||||
Via 2-S8TM,VIM2,
|
||||
Via 2-PLM,VIM2,X
|
||||
Metal 3-TLM,MM3,
|
||||
Metal 3-S8TM,MM3,
|
||||
Metal 3-PLM,MM3,X
|
||||
Pad Via,VIPDM,
|
||||
Via3-PLM,VIM3,X
|
||||
Inductor-TLM,INDM,
|
||||
Metal 4,MM4,X
|
||||
Via4,VIM4,X
|
||||
Metal 5,MM5,X
|
||||
Nitride Seal Mask,NSM,X
|
||||
Pad (scribe protect),PDM,X
|
||||
Pad (scribe unprotect),PDM,
|
||||
Polyimide,PMM,
|
||||
Polyimide_ExtFab,PMM[E],
|
||||
Pad&Polyimide_ExtFab,PDMM[E],
|
||||
DECA PBO,PBO,X
|
||||
Cu Inductor/Redist.,CU1M,X
|
||||
Polyimide 2 (2),PMM2,X
|
||||
Under Bump Metal,UBM,
|
||||
Bumps,BUMP,
|
||||
|
|
|
@ -0,0 +1,15 @@
|
|||
Masks
|
||||
=====
|
||||
|
||||
The :download:`masks.csv file <./masks.csv>` provides a raw information for the
|
||||
mask layers (name, acronym, usage) currently used found on 130nm processes at
|
||||
SkyWater.
|
||||
|
||||
The masks which are used on the SKY130 technology node (that this PDK supports)
|
||||
are marked.
|
||||
|
||||
.. csv-table:: Table - Masks
|
||||
:file: masks.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
:widths: 70, 20, 10
|
||||
|
|
@ -0,0 +1,64 @@
|
|||
Parasitic Layout Extraction
|
||||
===========================
|
||||
|
||||
This table list layers and contacts included in SPICE models, and parasitic layers include in the AssuraLayout Extraction.
|
||||
|
||||
The modeled columns indicate sheets and contacts that are parasitic resistance/capacitance included in the model extraction measurements.
|
||||
|
||||
The CAD columns indicate sheets and contacts that are parasitics included in the schematic/layout RCX from Assura.
|
||||
|
||||
.. csv-table:: Parasitic Extraction Table
|
||||
:file: rcx/rcx-all.csv
|
||||
:header-rows: 2
|
||||
:stub-columns: 1
|
||||
|
||||
|
||||
.. note:: The models includes M1/M2 capacitance. As a result of RCX extraction limitation M1/M2 routing over the varactor will have no capacitance extraction.
|
||||
|
||||
Routing and placement of devices over or under Precision resistors (xhrpoly_X_X) should be avoided.
|
||||
|
||||
The parasitic capacitance between 3-terminal MIMC and any routing/devices is not included in layout RCX, except M3 by 1 snap grid width.
|
||||
|
||||
No artificial fringing capacitance is extracted for MIMC M2/M3 due to CAD algorithm after CAPM sizing.
|
||||
|
||||
The parasitic capacitance between Precision resistors (xhrpoly_X_X) and any routing/devices is not included in layout RCX.
|
||||
|
||||
S8Q-5R is not supported for RF ESD diode RCX blocking.
|
||||
|
||||
The ``areaid:substratecut`` will be extracted as a 0.123 ohm two terms resistor.
|
||||
|
||||
Resistance Rules
|
||||
----------------
|
||||
|
||||
.. todo:: This table should be rendered like the periphery rules.
|
||||
|
||||
.. csv-table:: Table of resistance rules
|
||||
:file: rcx/resistance.csv
|
||||
:header-rows: 2
|
||||
:stub-columns: 1
|
||||
|
||||
|
||||
Capacitance Rules
|
||||
-----------------
|
||||
|
||||
.. todo:: This table should be rendered like the periphery rules.
|
||||
|
||||
.. csv-table:: Table of capacitance rules
|
||||
:file: rcx/capacitance.csv
|
||||
:header-rows: 2
|
||||
:stub-columns: 1
|
||||
|
||||
|
||||
Discrepencies
|
||||
-------------
|
||||
|
||||
Non-precision poly resistors
|
||||
These resistors do not extract capacitance to substrate.
|
||||
|
||||
This needs to be accounted for manually by using ICPS_0150_0210 (cap per perimeter), and ICPS_2000_4000 (cap per area).
|
||||
|
||||
Un-shielded VPP's
|
||||
Any routing above an un-shielded VPP will not be extracted.
|
||||
|
||||
The impact of this on total capacitance and parasitic capacitance is already comprehended in the model corners, however, cross-talk is not modeled. Also, parasitic cap is routed to ground and this may not be ideal for the scenario.
|
||||
The parasitic cap can be estimated using RescapWeb.
|
||||
|
|
@ -0,0 +1,30 @@
|
|||
,General(CAP.-)
|
||||
.X.1,No capacitance is extracted due to contacts. (This is a generic layout extraction tool limitation.)
|
||||
|
||||
,MOS Devices (MOS.-)
|
||||
.mos.1,area between poly and diff should not have capacitance extracted.
|
||||
.mos.2,li within .055um will not have fringing capacitance (npcon.4 = 0.055 for S8)
|
||||
.mos.3,there will be no fringing caps between gates ( as capacitance is shielded by the LICON and MCON).
|
||||
.mos.4,All 20V NMOS ISO DEFETs will have the parasitic diodes included in the models.
|
||||
.mos.5,All 20V NMOS ISO DEFETs will have the parasitic diode included in the models.,This model also includes the 5th terminal Drain-Psub diode (DeepNwell - Psub).
|
||||
.mos.6,All 20V PMOS DEFETs will have the parasitic DeepNwell-Psub diode included in the CAD extraction.
|
||||
.mos.7,The only 20V DEFET instance parameter that the model uses from CAD extraction is m-factor.,The model will over-write all other instance parameters from CAD extraction.
|
||||
|
||||
,Resistors (RES.-)
|
||||
.res.1,short devices must not have capacitance calculated across the device.
|
||||
.res.2,fuse devices must have capacitance extracted.
|
||||
.res.3,poly resistors that are not the precision poly resistors (xhrpoly_X_X) must have capacitance extracted.
|
||||
.res.4,metops that are merged must have capacitance extracted.
|
||||
.res.5,parasitic resistors for diff/nwell must have the junction diode extracted.
|
||||
.res.6,Poly precision resistors must not have the poly-psub parasitic capacitance extracted (RCX should also exclude head/tail poly-psub capacitance).
|
||||
.res.7,"For Poly precision resistors xhrpoly_X_1, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 0.50 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
|
||||
.res.8,"For Poly precision resistors xhrpoly_X_2, the device recognition layer is defined by growing the poly.rs AND rpm.dg layers 1.18 um(head/tail distance from ID layer) in all directions. Poly-Field/Diff/Well, and Poly-Poly, Poly-Li will not have capacitance extracted inside this device recognition layer."
|
||||
|
||||
,Capacitors (PASSIVES.-)
|
||||
.cnwvc.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.465u away from device\n recognition layer (as defined in LVS table of TDR)"
|
||||
.cmimc.1,"capacitance will not be extracted between M2 to field, diff, Poly, Li, M1 up to 0.14u away from device\n recognition layer (intersection of M2 overlapping CAPM that's connected to VIA2, 3-terminal MiM only)"
|
||||
.crfesd.1,"capacitance will not be extracted for field, diff, Poly, Li, M1, M2 up to 0.4u away from device recognition layers (diode terminals)"
|
||||
.xcmvpp.1," For Cap extraction of xcmvpp11p5x11p7_polym50p4shield, the metal5 exposed for metal5-metal5 capacitance extraction is an extra 0.4um from the extraction of xcmvpp11p5x11p7_polym5shield. For any layer below metal5, the capcitance extraction of xcmvpp11p5x11p7_polym50p4shield is the same as xcmvpp11p5x11p7_polym5shield (Note: for the unit cel xcmvpp11p5x11p7_polym50p4shield metal5 is pulled in 0.4um from the cell edge)"
|
||||
|
||||
,Bipolar Devices
|
||||
,none
|
||||
|
Can't render this file because it has a wrong number of fields in line 9.
|
|
|
@ -0,0 +1,25 @@
|
|||
Name Description Model Structure Modeled RX Actual CAD RX RX Discrepancy Modeled CX Actual CX CX Discrepancy
|
||||
Notes Contacts Sheets Contacts Sheets Sheet Sheet
|
||||
All Periphery FETs mXXXX d g s b w l m ad as pd ps nrd nrs none diff(min) licon/mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3 li-negligible
|
||||
20V NDEFETs NONISO xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3 li-negligible
|
||||
20V NDEFETs ISO xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li/sky130_fd_pr__model__parasitic__diode_ps2dn li/m1/m2-m3 li-negligible
|
||||
20V PDEFETs xXXXX d g s b w l m ad as pd ps nrd nrs none diff(min)/licon mcon/vias diff(ext)/poly/li/m1/m2-m3 none poly/licon/li li/m1/m2-m3/sky130_fd_pr__model__parasitic__diode_ps2dn__hv li-negligible
|
||||
Cell FETs NOT EXTRACTED FROM LAYOUT N/A N/A N/A N/A N/A N/A N/A N/A
|
||||
All Diodes dXXXX n1 n2 area pj licon diff licon/mcon/vias poly/li/m1/m2-m3 licon-negligible Junction li/m1/m2-m3 none
|
||||
RF ESD Diodes xesd_XXXX n1 n2 area pj licon/mcon/via li/m1/m2 via2 m3 none li/m1/m2 m3 none
|
||||
pnp_05v5 Parasitic PNP qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W0p68L0p68 m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
|
||||
Parasitic PNP (5X) qXXXX nc nb ne ns sky130_fd_pr__pnp_05v5_W3p40L3p40 m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
|
||||
npn_05v0 Parasitic NPN qXXXX nc nb ne ns sky130_fd_pr__npn_05v5 m licon/mcon diff/li mcon/vias li/m1/m2-m3 li/mcon-neglible na li/m1/m2-m3 none
|
||||
res_generic_XXX Non-precision Resistors rXXXX a b l w m none sheet layer licon/mcon/vias none (no sheet resistance where sheet layer & res id layer intersect) none none junction/li/m1/m2-m3 parasitic capacitance to substrate (tool limitation)
|
||||
res_iso_pw Isolated Pwell Resistor xXXXX pwres r0 r1 b l w m licon/mcon pwell/li vias m1/m2-m3 none none junction/m1/m2-m3 li-negligible
|
||||
res_high_XXX Precision poly resistor xXXXXX hrpoly_X_X r0 r1 b l w m licon/mcon poly/li via m1/m2-m3 none poly-sub m1/m2-m3 li-negligible
|
||||
cap_mim_XXXX MIM Capacitor (2-terminal) xXXXX sky130_fd_pr__cap_mim_m3_2 c0 c1 w l m via2 m3 N/A poly/li/m1/m2 m2 (of the device) -negligible capm-m2 li/m1/m2-m3 routing layers underneath device
|
||||
cap_mim_XXXX MIM Capacitor (3-terminal) xXXXX sky130_fd_pr__model__cap_mim c0 c1 b w l m via2 m3 N/A poly/li/m1/m2 m2 (of the device) -negligible m2-sub/capm-m2 (1) Carea of M2-sub (non-overlap CAPM w/ 0.14um upsize) (2) M3 Cap by 1 snap grid width none
|
||||
cap_vpp_XXXX Vertical Parallel Plate Cap xXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b m No special RCX implementation for VPP required since black-box LVS will be used mcon/via li/m1/m2 none (black box LVS) none (black box LVS) none li/mcon//m1/via/m2 none (black box LVS) Parasitic capacitance to routing above
|
||||
cap_vpp_XXXX Vertical Parallel Plate Cap over MOSCAP xXXXX sky130_fd_pr__cap_vpp_XXXXX c0 c1 b m mcon/via li/m1/m2 none (black box LVS) none (black box LVS) none li/mcon//m1/via/m2 none (black box LVS) Parasitic capacitance to routing above
|
||||
cap_vpp_XXXX 4-terminal Vertical Parallel Plate Cap (M3 Shielded) xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m= licon/mcon/via poly/li/m1/m2 via3/via4 m3/m4/m5 none poly/licon/li/mcon/m1/via/m2/m3 m3-substrate (not m3-m2), neighboring metal to VPP metal none
|
||||
cap_vpp_XXXX 4-terminal Vertical Parallel Plate Cap (M5 Shielded) xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b term4 m= licon/mcon/via/via2/via3 poly/li/m1/m2/m3/m4 via4 m5 none poly/licon/li/mcon/m1/via/m2/m3/m4/m5 neighboring metal to VPP metal none
|
||||
cap_vpp_XXXX 3-terminal Vertical Parallel Plate Cap xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= mcon/via li/m1/m2 via2/via3/via4 m3/m4/m5 none li/mcon/m1/via/m2 neighboring metal to VPP metal Parasitic capacitance to routing above
|
||||
cap_vpp_XXXX 3-terminal Vertical Parallel Plate Cap xXXXXX sky130_fd_pr__cap_vpp_XXXX c0 c1 b m= mcon/via/via2 li/m1/m2/m3 via3/via4 m4/m5 none li/mcon/m1/via/m2/via2/m3 neighboring metal to VPP metal none
|
||||
cap_var_XXXX Varactor xXXXXX sky130_fd_pr__cap_var_XXXX c0 c1 b l w m licon/mcon/via diff/poly/li/m1/m2 via2 m3 none poly/li/m1/m2 nwdiodemodel/m3* none
|
||||
Inductor xXXXXX xindXXXX t1 t2 body No special RCX implementation for inductor required since black-box LVS will be used via m2/Cu Nothing extracted within inductor.dg layer none m2/via/Cu Nothing extracted within inductor.dg layer none
|
||||
|
|
|
@ -0,0 +1,26 @@
|
|||
,General (RES.-)
|
||||
.X,Parasitic resistance is not extrated under a sheet layer with it's corresponding res.id layer.
|
||||
|
||||
,Sheet Resistance (SR.-)
|
||||
.X,Calibre now extracts deltaW by bucketing the sheet rho based on different widths.,The accuracy of each bucket must be within 2% of the Sheet Rho Calc using deltaW.
|
||||
.met3,Parasitic resistance is calculated for all metal3 (if metal3 exists for the specific technology)
|
||||
.met2,Parasitic resistance is calculated for all metal2.
|
||||
.met1,Parasitic resistance is calculated for all metal1 with the exception of varactor which follow rule SR.xcnwvc.1
|
||||
.li1,Parasitic resistance is calculated for all li1.
|
||||
.poly.1,Parasitic resistance on gates is calculated to the center of the gate.
|
||||
.poly.2,Parasitic resistance for poly is not extracted beyond the device terminal. The device terminal for all devices but MOS is at the edge of the poly. Note: This means that parasitic resistance is not extracted for poly that is part of an LVS capacitor or LVS resistor. The LVS capacitors have poly in the model.
|
||||
.diff.1,Parasitic resistance is not extracted for any diffusion regions.
|
||||
.diff.2,Extract NRD/NRS for MOSFETs (except extendedDrain Fets) per the equations defined in USC-206. NRD/NRS for the n-type ESD devices must include the ntap enclosed in the source/drain ndiff hole NRD/NRS for the p-type ESD devices must include the ptap enclosed in the source/drain pdiff hole.
|
||||
.xnwvc.1,Inside the Varactor device boundry (see rule PASSIVES.cnwvc.1) all layers listed in the model (m1 and below) will not have resistance extracted.
|
||||
|
||||
,contact-to-gate space (CT.-)
|
||||
.via,All vias will have parasitic resistance extracted.
|
||||
.mcon,All mcons will have parasitic resistance extracted.
|
||||
.licon.1,All licons that are connected to Poly and not connected to the poly of the xhrpoly_X_X device should have resistance extracted.
|
||||
.licon.2,All licons that are connnected to non-precision resistors will have resistance extracted.
|
||||
.licon.3,All licons that are connected to FETs will be extracted by RCX.
|
||||
.licon.4,All licons on diff of PNP/NPN will be considered part of the device model.
|
||||
.licon.5,All licons on tap of PNP/NPN will be considered part of the device model.
|
||||
.licon.6,All licons on non-PNP tap regions will have parasitic resistance extracted.
|
||||
.hrpoly.1,"All licons and mcons that are part of the hrpoly resistor will not have parasitic resitance extracted, these contacts are in the models."
|
||||
.pwres.1,"All licons and mcons that are part of the pwell resistor will not have parasitic resitance extracted, these contacts are in the models."
|
||||
|
Can't render this file because it has a wrong number of fields in line 5.
|
|
|
@ -0,0 +1,42 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
import csv
|
||||
import os
|
||||
import pprint
|
||||
import sys
|
||||
|
||||
__dir__ = os.path.dirname(os.path.abspath(__file__))
|
||||
|
||||
TSV_FILE = os.path.join(__dir__, "rcx-all.tsv")
|
||||
|
||||
|
||||
def main(arg):
|
||||
rows = []
|
||||
with open(TSV_FILE, newline='') as csvfile:
|
||||
reader = csv.reader(csvfile, delimiter='\t')
|
||||
for r in reader:
|
||||
rows.append(list(c.strip() for c in r))
|
||||
|
||||
rowlen = max(len(r) for r in rows)
|
||||
for r in rows:
|
||||
while len(r) < rowlen:
|
||||
r.append('')
|
||||
|
||||
clen = [0] * rowlen
|
||||
for i, _ in enumerate(clen):
|
||||
clen[i] = max(len(r[i]) for r in rows)
|
||||
|
||||
for r in rows:
|
||||
for i, m in enumerate(clen):
|
||||
r[i] = r[i].ljust(m)
|
||||
|
||||
rows.insert(1, ['-'*m for m in clen])
|
||||
|
||||
for r in rows:
|
||||
print("|", " | ".join(r), "|")
|
||||
|
||||
return 0
|
||||
|
||||
|
||||
if __name__ == "__main__":
|
||||
sys.exit(main(sys.argv))
|
||||
|
|
@ -0,0 +1,34 @@
|
|||
Summry of Key Periphery Rules
|
||||
=============================
|
||||
|
||||
.. csv-table:: Table F3a: Front end layers (Low Voltage Devices)
|
||||
:file: summary/table-f3a-font-end-low-voltage.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. csv-table:: Table F3b: Front end layers (High Voltage Devices)
|
||||
:file: summary/table-f3b-font-end-high-voltage.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
Manual merge means that features below min. space should be manually merged by drawing.
|
||||
|
||||
.. csv-table:: Table F3c: Back end layers for S8D* flow
|
||||
:file: summary/table-f3c-back-end-high-S8Dx.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. csv-table:: Table F3d: Back end layers for S8T* flow
|
||||
:file: summary/table-f3d-back-end-high-S8Tx.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. csv-table:: Table F4: Connectivity of Drawn and Mask Layers (1)
|
||||
:file: summary/table-f4-connectivity-of-drawn-and-mask.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. csv-table:: Table F5: Device Connectivity Table
|
||||
:file: summary/table-f5-device-connectivity.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
|
@ -0,0 +1,11 @@
|
|||
Layer,CD,nwell,,diff,,tap,,n/psdm,,poly,,npc,,licon,Manual,,
|
||||
Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,merge ?,,
|
||||
nwell,0.840,1.270,X,X,X,X,X,X,X,X,X,X,X,X,Yes,,
|
||||
diff,0.150,0.340,0.180,0.270,X,X,X,X,X,X,X,X,X,X,-,,
|
||||
tap,0.150,0.130,0.180,0.270,-,0.270,X,X,X,X,X,X,X,X,-,,
|
||||
n/psdm,0.380,-,-,0.130,0.130,0.130,0.130,0.380,X,X,X,X,X,X,Yes,,
|
||||
poly on diff,0.150,-,-,-,-,0.300,-,-,-,0.210,X,X,X,X,-,,
|
||||
poly on field,0.150,-,-,0.075,-,0.055,-,-,-,0.210,X,X,X,X,-,,
|
||||
npc,0.270,-,-,-,-,-,-,-,-,0.090,X,0.270,X,X,Yes,,
|
||||
licon,0.170,-,-,-,0.04/ 0.06,-,0.000,-,-,0.055,-,0.090,-,0.170,-,,
|
||||
poly_licon,0.170,-,-,0.190,illegal,0.190,illegal,-,-,-,0.080,-,0.100,0.170,-,,
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
Layer,CD,nwell,,diff,,tap,,poly,,lvom,,Manual,,,,,
|
||||
Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,merge ?,,,,,
|
||||
hnwell,0.840,2.000,X,X,X,X,X,X,X,X,X,Yes,,,,,
|
||||
hvi,0.600,0.700,-,0.180,0.180,0.180,0.180,-,-,0.700,X,Yes,,,,,
|
||||
hdiff,0.290,0.430,0.330,0.300,X,X,X,X,X,X,X,-,,,,,
|
||||
htap,0.150,0.430,0.330,,-,0.270,X,X,X,X,X,-,,,,,
|
||||
HV poly,0.500,-,-,0.075,-,0.055,-,0.210,X,-,-,-,,,,,
|
||||
|
|
|
@ -0,0 +1,10 @@
|
|||
Layer,CD,licon,,li1,,mcon,,metal1,,via,,metal2,,via2,,metal3,
|
||||
Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc
|
||||
li1,0.170,undefined,0.000,0.170,X,X,X,X,X,X,X,X,X,X,X,X,X
|
||||
mcon,0.170,-,-,-,0.000,0.190,X,X,X,X,X,X,X,X,X,X,X
|
||||
metal1,0.140,-,-,-,-,-,0.03/ 0.06,0.140,X,X,X,X,X,X,X,X,X
|
||||
via,0.150,-,-,-,-,-,-,-,0.055 / 0.085,0.170,X,X,X,X,X,X,X
|
||||
metal2,0.140,-,-,-,-,-,-,-,-,-,0.055 / 0.085,0.140,X,X,X,X,X
|
||||
via2,0.280,-,-,-,-,-,-,-,-,-,-,-,0.040,0.280,X,X,X
|
||||
metal3,0.360,-,-,-,-,-,-,-,-,-,-,-,-,-,0.045 / 0.07,0.360,X
|
||||
,All enclosures in tables are nominal and do not apply to butting edges or corners.,,,,,,,,,,,,,,,,
|
||||
|
|
|
@ -0,0 +1,10 @@
|
|||
Layer,CD,licon,,li1,,mcon,,metal1,,via,,metal2,,via2,,metal3,
|
||||
Parameter,width,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc,spc,enc
|
||||
li1,0.170,undefined,0.000,0.170,X,X,X,X,X,X,X,X,X,X,X,X,X
|
||||
mcon,0.170,-,-,-,0.000,0.190,X,X,X,X,X,X,X,X,X,X,X
|
||||
metal1,0.140,-,-,-,-,-,0.03/ 0.06,0.140,X,X,X,X,X,X,X,X,X
|
||||
via,0.150,-,-,-,-,-,-,-,0.055 / 0.085,0.170,X,X,X,X,X,X,X
|
||||
metal2,0.140,-,-,-,-,-,-,-,-,-,0.055,0.140,X,X,X,X,X
|
||||
via2,0.280,-,-,-,-,-,-,-,-,-,-,-,0.190,1.200,X,X,X
|
||||
metal3,2.500,-,-,-,-,-,-,-,-,-,-,-,-,-,0.310,2.500,X
|
||||
,All enclosures in tables are nominal and do not apply to butting edges or corners.,,,,,,,,,,,,,,,,
|
||||
|
|
|
@ -0,0 +1,23 @@
|
|||
Table F4: Connectivity of Drawn and Mask Layers (1),,,,,,,,,,,,,,,,,
|
||||
,,,,,,,,,,,,,,,,,
|
||||
,Deep N Well,N Well,Diff,Tap,Poly,Li1,Capm,Met1,Met2,Met3,Met4,Met5,rdl,,,,
|
||||
Deep N Well,N/A,,,,,,,,,,,,,,,,
|
||||
N Well,Over,N/A,,,,,,,,,,,,,,,
|
||||
Diff,X,X,N/A,,,,,,,,,,,,,,
|
||||
Tap,X,Over,X,N/A,,,,,,,,,,,,,
|
||||
Poly,X,X,X,X,N/A,,,,,,,,,,,,
|
||||
Li1,X,X,Licon1,Licon1,Licon1 AND Npc,N/A,,,,,,,,,,,
|
||||
Capm,X,X,X,X,X,X,N/A,,,,,,,,,,
|
||||
Met1,X,X,X,X,X,Mcon,X,N/A,,,,,,,,,
|
||||
Met2,X,X,X,X,X,X,X,Via,N/A,,,,,,,,
|
||||
Met3,X,X,X,X,X,X,Via2,X,Via2,N/A,,,,,,,
|
||||
Met4,X,X,X,X,X,X,X,X,X,Via3,N/A,,,,,,
|
||||
Met5,X,X,X,X,X,X,X,X,X,X,Via4,N/A,,,,,
|
||||
rdl,X,X,X,X,X,X,X,X,X,X,X,(pad AND pmm) for s8pir/s8pr2-10r flows (1),N/A,,,,
|
||||
bump,X,X,X,X,X,X,X,X,X,X,X,X,pi2 AND ubm,,,,
|
||||
,,,,,,,,,,,,,,,,,
|
||||
(1) All layerr drawn except pmm which is created as cpmm:mask over bond pads or converted into cpbo:mask,,,,,,,,,,,,,,,,,
|
||||
(2) Entries in this table show the layer (or combination of layers) that act as connecting layers listed in the row/column ,,,,,,,,,,,,,,,,,
|
||||
headings. An X indicates that there is no direct connection between these layers. N/A is entered along the diagonal;,,,,,,,,,,,,,,,,,
|
||||
Over- Layers contacted by overlapping. A layer is always connected to itself.,,,,,,,,,,,,,,,,,
|
||||
"(3) (Met5 AND pad AND rdl) should have one of the following sizes for LVS to work with WLCSP option: 60x60, 50x70, 60x80, and 80x80",,,,,,,,,,,,,,,,,
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
Devices,LVS,Latch up,,Soft,,,,,,,,,,,,,
|
||||
Transistors,open,open,,open,,,,,,,,,,,,,
|
||||
resistor,open,open,,open,,,,,,,,,,,,,
|
||||
diode,open,open,,open,,,,,,,,,,,,,
|
||||
pnp,open,open,,open,,,,,,,,,,,,,
|
||||
Inductor,open,short,,open,,,,,,,,,,,,,
|
||||
capacitors,open,open,,open,,,,,,,,,,,,,
|
||||
|
|
|
@ -0,0 +1,14 @@
|
|||
WLCSP Rules
|
||||
===========
|
||||
|
||||
.. TODO: These should be formatted in the same way the periphery rules are.
|
||||
|
||||
.. csv-table:: Amkor WLCSP
|
||||
:file: wlcsp/amkor.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
||||
.. csv-table:: DECA WLCSP
|
||||
:file: wlcsp/deca.csv
|
||||
:header-rows: 1
|
||||
:stub-columns: 1
|
||||
|
|
@ -0,0 +1,31 @@
|
|||
Allowed pitch,,Supported flows,,Allowed pitch,
|
||||
400 um,500 um, s8p-5r\ns8p-10r*\ns8pf-10r*\ns8pfn-20r*\ns8p12-10r*\ns8spf-10r*,,400 um,500 um
|
||||
(pi1.-.-),(pi1_500.-.-),1st polyimide layer for WLCSP,,,
|
||||
,,Function: Opens over the pad openings; Allows RDL layer to connect to top metal,,,
|
||||
1,1,Min width of pi1 (for parallel opposite edges),,35.00,35.00
|
||||
2,2,Min spacing between pi1,,20.00,20.00
|
||||
3,3,pi1 must be enclosed by pad by atleast,,7.50,7.50
|
||||
(rdl.-),(rdl_500.-),Re-distribution layer,,,
|
||||
,,Function: Re-distribution layer connects the top metal from the customer to the bumps,,,
|
||||
1,1,Min width of rdl (for parallel opposite edges),,10.00,10.00
|
||||
2,2,min spacing between two rdl,,10.00,10.00
|
||||
3,3,pi1 must be enclosed by rdl by atleast,,10.00,10.00
|
||||
(pi2.-.-),(pi2_500.-.-),2nd polyimide layer for WLCSP,,,
|
||||
,,Function: 2nd polyimide layer acts as a via between RDL and UBM,,,
|
||||
1,1,Min width of pi2 (for parallel opposite edges),,170.00,220.00
|
||||
3,3,"Min spacing, no overlap, between pi1 and pi2",,25.00,25.00
|
||||
(ubm.-.-),(ubm_500.-.-),Under bump metal,,,
|
||||
,,Function: Layer added underneath the bump balls,,,
|
||||
1,1,Min width of ubm (for parallel opposite edges),,215.00,250.00
|
||||
3,3,pi2 must be enclosed by ubm by atleast,,15.00,15.00
|
||||
4,4,ubm must be enclosed by rdl by atleast,,10.00,10.00
|
||||
5,5,"Min spacing, no overlap, between pi1 and ubm",,10.00,10.00
|
||||
6,6,Min spacing between center of ubm and outer edge of the seal ring,,155.00,195.00
|
||||
(bump.-.-),(bump_500.-.-),Bump balls for WLCSP,,,
|
||||
,,Function: WLCSP bump balls,,,
|
||||
1,1,Min width of bump (for parallel opposite edges),,261.00,310.00
|
||||
2,2,Min/Max pitch spacing between bump (center to center),,400.00,500.00
|
||||
2a,2a,Min/Max pitch spacing between bump (center to center) across the scribe,NC,400.00,500.00
|
||||
3,3,Min spacing between bump and outer edge of the seal ring,,25.00,25.00
|
||||
4,4,Min size of Chip_extent overlapping bump.dg,,750 X 1000,1000 X 1000
|
||||
5,5,Max size of Chip_extent overlapping bump.dg,,6800 X 6800,6800 X 6800
|
||||
|
|
|
@ -0,0 +1,31 @@
|
|||
(cpbo.-.-),1st polyimide (mask),,
|
||||
,Function: Opens over the pad openings; Allows RDL layer to connect to top metal,,
|
||||
wlcsp.1,Min cpbo diameter over bond pad passivation opening,,20.00
|
||||
wlcsp.2,Min bond pad passivation opening to create cpbo,,35.00
|
||||
wlcsp.3,Min enclosure of cpbo over bond pad by pad:dg,,7.50
|
||||
(rdl.-),Re-distribution,,
|
||||
,Function: Re-distribution layer connects the top metal from the customer to the bumps,,
|
||||
x.1,"Polymer 1 via and RDL1 capture pad should be designed as large as possible. The shape can be a circle, octagon, oblong, or a square with rounded corners. The via is not required to be centered within the passivation opening. Any offset is acceptable as long as the minimum overlap design rules are met",,exempt x.3a
|
||||
x.2,"Fillet or “teardrop” is required between the trace and the RDL1 UBM capture pad to reduce stress and avoid 90°or acute angles which can cause over etching. If room permits, the fillet width shall be 90% of the RDL 1 UBM capture pad diameter and set back from pad shall be the same as the trace width.",,add teardrop
|
||||
x.3,"Trace width and spacing shall be made equal and maximized where possible for optimized manufacturability, reliability and improved electrical performance (minimum width and spacing shall be limited to a localized area).",,Best practice
|
||||
wlcsp.1,Min rdl pad diameter over bond pad,,40.00
|
||||
wlcsp.2,Min spacing between rdl and rdl larger than 30 um by 30 um and a run length > 60um,,15.00
|
||||
wlcsp.3,cpbo (with max width of 30x30 must be enclosed by rdl by at least ,,10.00
|
||||
(cpmm2.-.-),2nd polyimide,,
|
||||
,Function: 2nd polyimide layer acts as a via between RDL and UBM,,
|
||||
x.1,Capture pads are identified by (rdl and bump) enclosing pmm2,,
|
||||
wlcsp.1,"Min spacing, no overlap, between cpbo and cpi2 on different nets",,25.00
|
||||
wlcsp.2,Min enclosure of cpbo by cpmm2 (no straddle),,15.00
|
||||
wlcsp.3,Min cpmm2 pad diameter,,155.00
|
||||
wlcsp.4,Min diameter of rdl capture pad under cpmm2,,235.00
|
||||
wlcsp.5,Min enclosure of rdl by cpmm2,,15.00
|
||||
wlcsp.6,Minimum remaining fraction (polymer 2) size of full via size\nAdd a radius or chamfer on sharp corners of truncated 2nd polyimide via and corresponding RDL capture pad.,,0.5
|
||||
(ubm.-.-),Under bump metal,,
|
||||
,Function: Layer added underneath the bump balls,,
|
||||
1,Min width of ubm (for parallel opposite edges),,215.00
|
||||
2,pmm2 must be enclosed by ubm by atleast,,15.00
|
||||
3,Min spacing between center of ubm and outer edge of the seal ring,,250.00
|
||||
(bump.-.-),Bump balls for WLCSP,,
|
||||
,Function: WLCSP bump balls,,
|
||||
1,Min width of bump (for parallel opposite edges),,264.00
|
||||
2,Min/Max pitch spacing between bump (center to center w/2x snapGrid tolerance),,400.00
|
||||
|
Loading…
Reference in New Issue