19 lines
865 B
Plaintext
19 lines
865 B
Plaintext
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Layer / Design rule,CD,,space,,Comment
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Min HVNwell to any nwell space,,,2,,HVNwell_Nwell_SP
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Min HVDiff width,0.29,,,,HVDiff_CD
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Min HVDiff space,,,0.3,,HVDiff_SP
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Min HV Pmos gate width,0.5,,,,HVP_gate_CD
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Min space between HV poly,,,0.28,,HVPoly_SP
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Min HV Nmos gate width,0.37,,,,HVPoly_CD
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HV P+ Diff enclosure by Nwell,0.33,,,,HVPdiff_nwell_enc
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HV N+ diff space to Nwell,,,0.43,,HVNdiff_nwell_SP
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HV N+ tap enclosure by Nwell,0.33,,,,HVNtap_nwell_enc
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HV P+tap space to Nwell,,,0.43,,HVPtap_nwell_SP
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Photoresist tilted implant penetration,0.02,,,,HVPrPenetration
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Photoresist tilted implant blocking distance,0.013,,,,HVPrBlocking
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Min size of HVTip,0.1,,,,HVTipMinSize
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Extra CD tol for HVNTM to match Ram7 process,0.015,,,,HVNTMExtraCdTol
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Min HVDiff resistor width,0.29,,,,HVDiff_Res_CD
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High voltage n+-n+ or p+-p+,,,0.3,,HVDPTS15
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HV MOSFET channel length,0.5,,,,HVPCD
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