docs: Initial start on process design rules.
Updates and documentation originally improved and then release by Kevin Kelly <kevin.kelley@skywatertechnology.com> to Google for imported into the docutils RST format by Tim 'mithro' Ansell <tansell@google.com>. Signed-off-by: Kevin Kelley <kevin.kelley@skywatertechnology.com> Signed-off-by: Tim 'mithro' Ansell <tansell@google.com>
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@ -27,8 +27,8 @@ File "metal_stack.ps" Page 1
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<path d="M643,923 L643,779 1619,779 1619,923 z" fill="#cbf3f3" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#cbf3f3" />
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<path d="M643,715 L643,571 1619,571 1619,715 z" fill="#cbf3f3" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#cbf3f3" />
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<path d="M659,491 L659,283 1571,283 1571,491 z" fill="#cbf3f3" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#cbf3f3" />
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<g transform="matrix( 1 0 -0 1 579 27)" fill="#000000" >
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<text stroke="none" font-family="Times" font-size="40" ><tspan x="0" y="0">SkyWater Sky130A metal stack (not to scale!):</tspan>
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<g transform="matrix( 1 0 -0 1 950 27)" fill="#000000" >
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<text stroke="none" font-family="Times" font-size="40" ><tspan x="0" y="0">(Diagram not to scale!)</tspan>
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</text></g>
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<path d="M443,1483 L1619,1483 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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<path d="M931,1483 L931,1499 " fill="none" stroke-width="2" stroke-linejoin="bevel" stroke-linecap="round" stroke="#000000" />
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Before Width: | Height: | Size: 54 KiB After Width: | Height: | Size: 54 KiB |
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@ -3,6 +3,8 @@
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.. toctree::
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:hidden:
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Design Rules <rules>
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versioning
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Current Status <status>
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known_issues
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@ -0,0 +1,10 @@
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SkyWater SKY130 Process Design Rules
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====================================
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.. toctree::
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:caption: Process Design Rules
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:name: rules
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:maxdepth: 2
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Introduction <rules/background>
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Design Rule Criteria & Assumptions <rules/assumptions>
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@ -0,0 +1,167 @@
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Criteria & Assumptions
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======================
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Process Stack Diagram
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---------------------
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.. image:: ../_static/metal_stack.svg
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:width: 100%
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:alt: SkyWater SKY130 Process Stack
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General
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-------
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.. csv-table:: Table 1 - General
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:file: assumptions/01-general.csv
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:header-rows: 1
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:stub-columns: 1
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Minimum Critical Dimensions
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---------------------------
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.. csv-table:: Table 2 - Minimum CDs in Design or on Wafer, required by Technology (Core or Periphery)
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:file: assumptions/02-mins.csv
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:header-rows: 1
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:widths: 20, 20, 10, 10, 10, 10
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Semiconductor Criteria
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----------------------
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Basic Parameters
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~~~~~~~~~~~~~~~~
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.. csv-table:: Table 3a - Semiconductor Criteria - Basic Parameters
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:header-rows: 1
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:width: 100%
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:widths: 30, 10, 20, 10
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,Units,Value,Variable name
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n-well peak concentration,cm-3,6.00E+017,NWPCONC
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background concentration,cm-3,8.00E+14,NWBCONC
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y.char,um,0.43,NWYCHAR
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desired Nmin/Ns ratio,,0.9,NMINNSRATIO
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min n-well width to guarantee 90 % peak concentr.,um,0.55,MINNWWID
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p-well peak concentration,cm-3,4E+017,PWPCONC
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p-well peak coordinate,um,0.42,PWPCOORD
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y.char,um,0.13,PWYCHAR
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min. p-well width to guarantee 90 % peak concentr.,um,0.33,MINPWWID
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Junction Depths
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~~~~~~~~~~~~~~~
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.. csv-table:: Table 3b - Semiconductor Criteria - Junction Depths
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:header-rows: 1
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:width: 100%
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:widths: 30, 10, 10, 10, 10
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,Units,Vertical Feature,Vertical Space,Variable name
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Baseline: N-Well,um,1.1, ,NWVDIM
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P-Well,um,0.75,,PWVDIM
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N-w/P-w junction (from drawn edge),um,*,0.034,WELLJCT
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N+ or P+ S/D (XJ),um,0.1,0.06,JCTD / LD
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Max (N+ or P+ S/D outdiff.) next to isol. edge,um,,0.007,LDST
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Max (N+ or P+ S/D outdiff.) next to isol. edge for 6 V reg. devices,,,0.05,LDST5
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N Tip (As),um, ,0.01,LDNTIP
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Other Width Criteria
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~~~~~~~~~~~~~~~~~~~~
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.. csv-table:: Table 3c - Semiconductor Criteria - Other Width Criteria
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:header-rows: 1
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:width: 100%
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:widths: 30, 10, 20, 10
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,Units,Value,Variable name
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Min. diff/tap width for reproducible resistivity,um,0.12,MINFWR
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Min. width to open a strip of tap between two diffs,um,0.34,SDM3
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"Max s/d diff width without contact, consistent w/Ram4,5,6",um,5.7,XMAXCON
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Punchthrough Criteria
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~~~~~~~~~~~~~~~~~~~~~
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.. csv-table:: Table 3d - Semiconductor Criteria - Minimum Spacing for 3.3V Punchthrough (1.8V devices)
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:header-rows: 1
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:width: 100%
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:widths: 30, 10, 20, 10
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,Units,Value,Variable name
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n-well - n-well ,um,0.835,NWPTS
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n+ - n+ or p+-p+,um,0.23,DPTS
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p+ in nwell to pwell,um,0.05,PPTS
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n+ in pwell to nwell,um,0.15,PNPTS
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Latch-up/ESD Criteria
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~~~~~~~~~~~~~~~~~~~~~
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.. csv-table:: Table 3e - Semiconductor Criteria - Latch-up/ESD Criteria
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:header-rows: 1
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:width: 100%
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:widths: 30, 10, 20, 10
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Minimum n+ or p+ - nwell spacing to prevent latch-up,um,0.23,NPNWLU
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Min n-well enclos. of tap to ensure bkdwn N-w/P-w before N+/P-w (ESD),um,0.04,XNWESD
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Max. overlap of n-well by p+ tap,um,0.06,XNWPTS
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Implant angles
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~~~~~~~~~~~~~~
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.. csv-table:: Table 3f - Semiconductor Criteria - Implant angles
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:header-rows: 1
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:width: 100%
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:widths: 30, 10, 10, 10, 10
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,Units,Angle,,Variable name
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High current,deg,0,0,HCIMPA
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Angle for tip implant ,deg,7,,TipAng
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Angle for HV tip implant ,deg,40,,HvTipAngle
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Twist angle for HV Tip ,deg,23,,HvTipTwist
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Physical Criteria
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-----------------
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.. csv-table:: Table 4 - Physical Criteria
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:file: assumptions/04-physical.csv
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:header-rows: 1
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:widths: 60, 10, 1, 10, 10, 10
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Laser Fuse Criteria
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-------------------
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.. csv-table:: Table 5 - Laser Fuse Criteria
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:file: assumptions/05-laser-fuse.csv
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:header-rows: 1
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:widths: 60, 10, 1, 10, 10, 10
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.. What happened to 6!?
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Other criteria and parameters
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-----------------------------
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.. csv-table:: Table 7 - Other criteria and parameters
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:file: assumptions/07-other.csv
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:header-rows: 1
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:widths: 60, 10, 1, 10, 10, 10
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Criteria for High Voltage FET
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-----------------------------
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.. csv-table:: Table 8 - Criteria for High Voltage FET
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:file: assumptions/08-hv.csv
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:header-rows: 1
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:widths: 60, 10, 1, 10, 10, 10
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Criteria for polyimide manufacturability
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----------------------------------------
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.. csv-table:: Table 9 - Criteria for polyimide manufacturability
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:file: assumptions/09-polyimide.csv
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:header-rows: 1
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:widths: 60, 10, 1, 10, 10, 10
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Criteria for VPP capacitor
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--------------------------
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.. csv-table:: Table 10 - Criteria for VPP capacitor
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:file: assumptions/10-vpp-capacitor.csv
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:header-rows: 1
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:widths: 60, 10, 1, 10, 10, 10
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@ -0,0 +1,4 @@
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Parameter,,Units,Value,,Variable name
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Space to Draw,, ,S8,,
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Grid Size - Drawn,,um,0.005,,GSF
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Approximate Scale Factor for R32 data,,,0.3,,sfr32
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@ -0,0 +1,59 @@
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Layer Name,,Feature Size,Space Size,Feature Name,Space Name
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Field Oxide,,0.14,0.27,FOMCD,FOMCDSP
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Deep N-Well,,3,6.3,DNMCD,DNMCDSP
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P-Well Block Mask,,0.84,1.27,PWBMCD,PWBMCDSP
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P-Well Drain Extended ,,0.84,1.27,PWDEMCD,PWDEMCDSP
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N-Well,,0.84,1.27,NWMCD,NWMCDSP
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High Vt PCh,,0.38,0.38,HVTPMCD,HVTPMCDSP
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Low Vt Nch,,0.38,0.38,LVTNMCD,LVTNMCDSP
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HLow VT PCh Radio,,0.38,0.38,HVTRMCD,HVTRMCDSP
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N-Core Implant,,0.38,0.38,NCMCD,NCMCDSP
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Tunnel Mask,,0.41,0.5,TUNMCD,TUNMCDSP
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ONO Mask,,0.41,0.5,ONOMCD,ONOMCDSP
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Low Voltage Oxide,,0.6,0.7,LVOMCD,LVOMCDSPCSMC
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Resistor Protect,,1.27,0.84,RPMCD,RPMCDSP
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Poly 1,Endcap/Gap,0.15,0.21,P1G,
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Poly 1,,N/A,0.14,P1MCD,P1MCDSP
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N-tip Implant,,0.84,0.7,NTMCD,NTMCDSP
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High Volt. N-tip,,0.7,0.7,HVNTMCD,HVNTMCDSP
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Lightly Doped N-tip,,0.7,0.7,LDNTMCD,LDNTMCDSP
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Nitride Poly Cut,,0.27,0.27,NPCMCD,NPCMCDSP
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P+ Implant,,0.38,0.38,PSDMCD,PSDMCDSP
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N+ Implant,,0.38,0.38,NSDMCD,NSDMCDSP
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Local Intr Cont.1,Slotted,0.17,0.17,LICM1SLCD,LICM1SLCDSP
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Local Intr Cont.1,Core,0.19,0.35,LICM1CD,LICM1CDSP
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Local Intrcnct 1,Core,0.14,0.14,LI1MCD,LI1MCDSP
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Local Intrcnct 1,,0.17,0.17,LI1MCD,LI1MCDSP
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Contact,,0.17,0.19,CTM1CD,CTM1CDSP
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Open Frame Mask,,N/A,N/A,OFMCD,OFMCDSP
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Metal 1,,0.14,0.14,MM1CD,MM1CDSP
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Metal 1 - Cu,,0.14,0.14,MM1_CuCD,MM1_CuCDSP
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Via,,0.15,0.17,VIMCD,VIMCDSP
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Via - Cu,,0.18,0.13,VIM_CuCD,VIM_CuCDSP
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Capacitor MiM,,2,0.84,CAPMCD,CAPMCDSP
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Metal 2,,0.14,0.14,MM2CD,MM2CDSP
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Metal 2 - Cu,,0.14,0.14,MM2_CuCD,MM2_CuCDSP
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Via 2-TNV,,0.28,0.28,VIM2CD,VIM2CDSP
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Via 2-S8TM,,0.8,0.8,VIM2CD,VIM2CDSP
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Via 2-PLM, ,0.2,0.2,VIM2CD,VIM2CDSP
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Via 2-Cu, ,0.21,0.18,VIM2_CuCD,VIM2_CuCDSP
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Metal 3-TLM,,0.36,0.36,MM3CD,MM3CDSP
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Metal 3-S8TM,,0.8,0.8,MM3CD,MM3CDSP
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Metal 3-PLM,,0.3,0.3,MM3CD,MM3CDSP
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Metal 3-Cu, ,0.3,0.3,MM3_CuCD,MM3_CuCDSP
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Pad Via,,1.2,1.27,VIPDMCD,VIPDMCDSP
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Via3-PLM,,0.2,0.2,VIM3CD,VIM3CDSP
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Via3-Cu, ,0.21,0.18,VIM3_CuCD,VIM3_CuCDSP
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Inductor-TLM,,2.5,2.5,INDMCD,INDMCDSP
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Metal 4,,0.3,0.3,MM4CD,MM4CDSP
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Metal 4-Cu, ,0.3,0.3,MM4_CuCD,MM4_CuCDSP
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Via4,,0.8,0.8,VIM4CD,VIM4CDSP
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Metal 5,All flows except S8PF*/S8PIR*,0.8,0.8,MM5CD,MM5CDSP
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Metal 5,S8PF*/S8PIR*,1.6,1.6,MM5CD,MM5CDSP
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Nitride Seal Mask,,3,4,NSMCD,NSMCDSP
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Pad (scribe protect),,2,1.27,PDMCD,PDMCDSP
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Polyimide,,5,15,PMMCD,PMMCDSP
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Polyimide_ExtFab,,5,15,PMM[E]CD,PMM[E]CDSP
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DECA PBO, ,10,10,PBOCD,PBOCDSP
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Cu Inductor/Redist.,,20,20,CU1MCD,CU1MCDSP
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Serifs,,0.1,0.1,SERCD,SERCDSP
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@ -0,0 +1,73 @@
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Material Thicknesses,,,Value (um),,Variable name
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field oxide (above silicon surface) ... underneath poly,,,0.07,,FOXSTEP
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"min. etch and fill capability for isolation, licon, and met1",,,0.15,,DEFC
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min. etch and fill capability for mcon,,,0.14,,CEFC
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min. etch and fill capability for via,,,0.18,,VEFC
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poly cap after SPE,,,0.2,,OVGTTH
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poly thickness,,,0.18,,POLYTH
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oxide spacer ,,,0.05,,SpThickn
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Pre-LI ILD thickness,,,0.5,,ILDTHICKN
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Licon1 etch angle (deg),,,10,,LICETANG
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Standard Licon bottom CD,,,0.08,,LBCD
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Mcon enclosure by Li,,,0,,mconLiEnclosure
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Via1 slope,,,0.02,,Via1Slope
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Oxide Bias for MM1,,,0.6,,BiasMM1
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Oxide Bias for MM2,,,0.6,,BiasMM2
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Oxide Bias for MM3,,,1.15,,BiasMM3
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Oxide Bias for MM4,,,1.15,,BiasMM4
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LI1 thickness for antenna ratio calculations,,,0.1,,LiThick
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Metal 1 thickness for antenna ratio calculations (S8D*),,,0.35,,Met1Thick
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Metal 2 thickness for antenna ratio calculations (S8D*),,,0.35,,Met2Thick
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Inductor thickness for antenna ratio calculation (S8D*),,,4,,IndmThick
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Metal 3 thickness for antenna ratio calculation (S8Q/SP8Q),,,0.8,,Met3thick_q
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Metal4 thickness for antenna ratio calculation (S8Q*/SP8Q),,,2,,Met4Thick_q
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Metal 3 thickness for antenna ratio calculation (S8P*/SP8P*),,,0.8,,Met3thick_p
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Metal4 thickness for antenna ratio calculation (S8P*/SP8P*),,,0.8,,Met4Thick_p
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Metal5 thickness for antenna ratio calculation (S8P*/SP8P* with 2um thick metal),,,2,,Met5Thick_p
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Metal5 thickness for antenna ratio calculation (S8P*/SP8P* with 1.2um thick metal),,,1.2,,Met5Thickp_12
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Metal 2 thickness for antenna ratio calculations (SP8T/S8T*),,,0.35,,Met2_Qthick
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Metal 3 thickness for antenna ratio calculations (S8T* other than S8TM*),,,0.85,,Met3_Qthick
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Metal 3 thickness for antenna ratio calculations (S8TM* flow),,,2,,Met3_TMthick
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Metal 3 thickness for antenna ratio calculations (SP8T flow),,,0.8,,Met3_SP8Tthick
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Photoresist thickness,,,1.14,,PRTHICKN
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Photoresist thickness for HV Tip Implants,,,0.3,,PrThickImplant
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Min width of tip implant opening,,,0.1,,minTip_impW
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NTM shadowing,,,0.16,,ntmShadowing
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HVNTM shadowing,,,0.232,,hvntmShadowing
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HVPTM shadowing,,,0.089,,hvptmShadowing
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pseudo-shadowing,,,0.045,,pseudoShadowing
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Channel length for low Vt PMOS,,,0.35,,lvtpmos_poly
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Width of the Low Leakage gate on each side of LowVt Pmos connected to power rails (requirement based on exp data),,,0.28,,LvtEnc_forPowerRail
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CD tolerance for PDM (3s),,,1,,PdmCD_tol
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Min process bias 3s tolerance,,,0.032,,PHTOL
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Min process bias 3s tolerance for poly,,,0.02,,PHP1TOL
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Minimum Space and Overlap,,,Value (um),,Variable name
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Minimum mcon overlap onto LI for reproducible contact resistance,,,0.12,,TCONOVLP
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Dogbone PR decay length (SRS 8/4/99),,,0.2,,DBPRDEC
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Bowing of rectangular contact (per edge) -- seal ring sizing,,,0.015,,TBOWINGSEAL
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Waffling / Pattern Density,,,Value,,Variable name
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S8 average FOM PD (extractions from logic device),,,0.45,,FOMPDAVG
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Size of small PD extraction box for rough tolerance (um),,,700,,SMALLPDBOX
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Size of large PD extraction box for rough tolerance (um),,,2000,,LARGEPDBOX
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Min pattern density for oxide,,,0.75,,OxideMinPD
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Min MM* PD range,,,0.3,,MMPDrange
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FOM 700um box PD tolerance for CMP (SOI8 PCR2) for all technologies,,,0.15,,FOM700TOL
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Stepping box shift as a percent of box size,,,0.5,,BOXSHIFT
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Maximum metal waffle drop pattern density in the frame,,,0.55,,PD_FrameWP
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Window size for frame waffle drop PD check,,,100,,WP_PDWINDOW
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Step size for frame waffle drop PD check,,,10,,WP_PDSTEP
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Other,,,Value,,Variable name
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Poly resistor width and spacing to reduce CD variation (um),,,0.33,,POLYRCD
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Poly resistor width and spacing to reduce CD variation (um),,,0.48,,POLYRSPC
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Spacing between slotted_licons (Not applicable when the two edges L= 0.19um),,,0.51,,LICM1SLSP1
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Precision resistor width to accommodate 6 contacts across,,,2.03,,PRECRESW
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Li resistor width (to drop one Licon w/o dogbones),,,0.29,,LIRESCD
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Correction factor for spacing to a wide metal line,,,2,,BIGMF
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Min spacing for created dnwell to pnp.dg (more restrictive than dnwell.4 rule),,,5,,cdnwPnpSpc
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"Min spacing between nwell and deep nwell on separate nets (Taken from dnwell.3 from S4* TDR *N plus rounded up, IGK request.)",,,6,,nwellDnwellSpc
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Min space between deep nwells used as photo diode (um),,,5,,PDDnwSpc
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Min space between dnwell (used for photo diode and other deep nwell (um),,,5.3,,PDDnwSpc1
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Min/Max width of nwell inside deep nwell (for photo diodes),,,0.84,,PDNwmCD
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Min/Max enclosure of nwell by deep nwell (for photo diode),,,1.08,,PDNwmDnwEnc
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Min/Max width of tap inside deep nwell (for photo diode),,,0.41,,PDTapCD
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Min/Max enclosure of tap by nwell inside deep nwell (for photo diode),,,0.215,,PDTapNwmEnc
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@ -0,0 +1,15 @@
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,,,Value (um),,Variable name
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Min. spac. of laser spot to diffused junction to ensure jct integrity,,,0.6,,XLASJUN
|
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Max. width of a metal fuse line that can be removed reliably,,,0.8,,FSW
|
||||
Min. L of met. fuse at which damage doesn't extend beyond ends,,,6.605,,FSLE
|
||||
Max. extension of met2 beyond fuse boundary,,,0.005,,FEXT
|
||||
Min. distance between laser spot and active junction,,,0.545,,LASJCT
|
||||
Standard contact bottom CD,,,0.09,,
|
||||
Positioning tolerance of laser spot (3 s),,,0.3,,LASMA
|
||||
Nominal effective laser spot diameter,,,3.5,,LASSPT
|
||||
Max. increase in spot diameter at max. distance from focus (3 s),,,0.9,,LASCDTOL
|
||||
Fuse melting radius,,,3.6,,MELTRAD
|
||||
Melting related crack size in ILD,,,0.36,,FUSECRACK
|
||||
Min space between fuse and any feature not connected to it,,,0.2,,MinFuseSpace
|
||||
Space between fuse and any unrelated layer,,,0.5,,SP_fuse_to_unrelated
|
||||
DC offset in some fuse rules,,,0.87,,LASDC1
|
||||
|
|
|
@ -0,0 +1,42 @@
|
|||
Layer / Design rule,CD,,space,,Comment
|
||||
MOSFET width,0.135,,,,FOMSE
|
||||
MOSFET width in standard cells,0.075,,,,FOMSESC
|
||||
Spacing of poly on field to diff,,,0.065,,PFDSE
|
||||
Spacing of poly on field to tap,,,0.005,,PFTSE
|
||||
Enclosure of tap by nwell for pwell res,,,0.22,,PTAP_NWL_SP
|
||||
Grid conversion rounding factor,,,0.005,,GRCF
|
||||
Licon enclosure rounding,,,0.02,,LICENCLR
|
||||
LI1CD add/drop,0.01,,0.04,,
|
||||
Huge metal X min. W and L,3,,,,HugeM
|
||||
Min Nsdm area ,0.265,,,,MinNsdmArea
|
||||
Min Psdm area,0.255,,,,MinPsdmArea
|
||||
Min N/Psdm hole area ,0.265,,,,MinNPsdmHole
|
||||
Large waffle size must be divisible by 4,7.2,,,,waffle_large
|
||||
P1M additional CD control,0.011,,,,P1MCDcontrol
|
||||
Li1 proximity correction,,,0.25,,LI1PROXSpace
|
||||
"Serif added to nwell convex corner (SXX-572, 573)",0.22,,,,NwellCvxSerif
|
||||
"Serif added to nwell concave corner (SXX-572, 573)",0.12,,,,NwellCveSerif
|
||||
NWM extension beyond nwell edge straddling de_nFet_source (for GSMC; QZM-133),0.075,,,,NvhvNwellExt
|
||||
Min enclosure of pad by pmm for Cu inductor (JNET-80) ,0,,,,padPMMEncInd
|
||||
Min enclosure of pmm by cu1m for Cu inductor (JNET-80) ,10.75,,,,pmmCu1mEncInd
|
||||
Min enclosure of pbo by cu1m per DECA 000348 Rev S,10,,,,pboCu1mEnc
|
||||
Min enclosure of pmm by pmm2 for radio flow in the die (JNET-80) ,13,,,,pmmPmm2EncInd
|
||||
Min enclosure of pmm by pmm2 inside frame,7.5,,,,pmmPmm2EncIndFrame
|
||||
Min space between pmm2 and Inductor.dg ,,,7.5,,pmm2IndSpc
|
||||
Min cu1m PD across full chip,0.35,,,,MinCU1Mpd
|
||||
Max cu1m PD across full chip,0.45,,,,MaxCU1Mpd
|
||||
Spacing between RDL and outer edge of seal ring,15,,,,RdlSealSpc
|
||||
Spacing between RDL and pmm2,6.16,,,,RdlPmm2Spc
|
||||
Enclosure of etest module in die by cpmm2,0,,,,EtestCpmm2Enc
|
||||
"Keepout of active, poly, li and metal to NSM (TCS-2253)",,,1,,NSMKeepout
|
||||
"3 um keepout of active, poly, li and metal to areaid.dt/areaid.ft (TCS-2253)",,,3,,NSMKeepout_3um
|
||||
pnp_emitter sizing (S8P GSMC flow),,,0.05,,PnpEmitterSzGSMC
|
||||
pnp_emitter sizing (other flows),,,0.03,,PnpEmitterSz
|
||||
MiM Capacitor aspect ration,20,,,,MiM_AR
|
||||
Min NCM space to be used to preserve NCM CL algorithm (avoid LVL error),,,1.27,,NCM_0LVL
|
||||
Min space of NCM between core and periphery due to existing layout restriction,,,0.96,,NcmCorePeriSP
|
||||
Multiplication factor,,,0.01,,S8LVconv
|
||||
Minimum scribe width,50,,,,scribew
|
||||
spacing of p-well outside deep n-well to deep n-well mask edge,,,0.12,,NWDNWENCL
|
||||
p-well in deep n-well to p-sub,,,1.2,,NWDNWOL
|
||||
Field oxide etchback after P1ME before implants,,,0.04,,WFDEL
|
||||
|
|
|
@ -0,0 +1,18 @@
|
|||
Layer / Design rule,CD,,space,,Comment
|
||||
Min HVNwell to any nwell space,,,2,,HVNwell_Nwell_SP
|
||||
Min HVDiff width,0.29,,,,HVDiff_CD
|
||||
Min HVDiff space,,,0.3,,HVDiff_SP
|
||||
Min HV Pmos gate width,0.5,,,,HVP_gate_CD
|
||||
Min space between HV poly,,,0.28,,HVPoly_SP
|
||||
Min HV Nmos gate width,0.37,,,,HVPoly_CD
|
||||
HV P+ Diff enclosure by Nwell,0.33,,,,HVPdiff_nwell_enc
|
||||
HV N+ diff space to Nwell,,,0.43,,HVNdiff_nwell_SP
|
||||
HV N+ tap enclosure by Nwell,0.33,,,,HVNtap_nwell_enc
|
||||
HV P+tap space to Nwell,,,0.43,,HVPtap_nwell_SP
|
||||
Photoresist tilted implant penetration,0.02,,,,HVPrPenetration
|
||||
Photoresist tilted implant blocking distance,0.013,,,,HVPrBlocking
|
||||
Min size of HVTip,0.1,,,,HVTipMinSize
|
||||
Extra CD tol for HVNTM to match Ram7 process,0.015,,,,HVNTMExtraCdTol
|
||||
Min HVDiff resistor width,0.29,,,,HVDiff_Res_CD
|
||||
High voltage n+-n+ or p+-p+,,,0.3,,HVDPTS15
|
||||
HV MOSFET channel length,0.5,,,,HVPCD
|
||||
|
|
|
@ -0,0 +1,13 @@
|
|||
Layer / Design rule,CD,,space,,Comment
|
||||
Enclosure of fuses by polyimide,12,,,,PimFuseEnc
|
||||
Enclosure of bondpad by polyimide (YUY-165),0.5,,,,PimPadEnc
|
||||
"Enclosure of pad:dg by PBO inside inductor capture pad, with DECA online monitoring",4.5,,,,PBOPadEnc
|
||||
Enclosure of pad:dg by PBO per standard DECA rules,7.5,,,,PBOPadEncDECA
|
||||
DECA PBO drawn-to-final process bias per side,0.5,,,,PBOProcBiasPerSide
|
||||
Polyimide CD tolerance,1,,,,PimCD_tol
|
||||
Min Pim width over pad openings,87,,,,PimOverPad_CD
|
||||
Polyimide slope (001-87400),,5.3,,,I_polyimide_slope
|
||||
Enclosure of polyimide by polymer tolerance,,7.7,,,Po_po_tol
|
||||
Min/Max enclosure of pad.dg inside M5RDL by pmm,0,,,,pmmM5RDLpadEnc
|
||||
Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc
|
||||
Enclosure of laser targets in the die by polyimide,30,,,,PimLaserEnc
|
||||
|
|
|
@ -0,0 +1,7 @@
|
|||
Layer / Design rule,CD,,space,,Comment
|
||||
Min width of capacitor:dg,4.38,,,,VppWidth
|
||||
Max width of unit capacitor:dg,8.58,,,,VppMaxWidth
|
||||
Min spacing between two capacitor:dg ,1.5,,,,VppSpc
|
||||
Min spacing of capacitor:dg to li1 or met1 or met2 or nwell,1.5,,,,VppOtherSPc
|
||||
Min enclosure of capacitor by nwell,1.5,,,,VppNwmEnc
|
||||
Min spacing of pmm to (rdl NOT (pad.dg sized by 0.5)),,,19.16,,pmmRDLspc
|
||||
|
|
|
@ -0,0 +1,15 @@
|
|||
Background
|
||||
==========
|
||||
|
||||
SKY130 is a mature 180nm-130nm hybrid technology developed by Cypress Semiconductor that has been used for many production parts. SKY130 is now available as a foundry technology through SkyWater Technology Foundry.
|
||||
|
||||
The technology is the 8th generation SONOS technology node (130nm).
|
||||
|
||||
The technology stack consists of;
|
||||
|
||||
- 5 levels of metal (`p` - penta)
|
||||
- Inductor or Inductor-Capable (`i`)
|
||||
- Poly resistor (`r`)
|
||||
- SONOS shrunken cell (`s`)
|
||||
- Supports 10V regulated supply (`10R`)
|
||||
|
||||
Loading…
Reference in New Issue