coriolis/crlcore
Jean-Paul Chaput fb4a7457a1 First basic version of ClockTree & Chip plugins.
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
    Clock Tree plugin:
    - It is strongly advised to use have 4 metal routing layers for the
      tree to work. Otherwise, problems can arise with the detailed
      routing (fully obstructed terminals).
    - H-Tree can only be build (for now) for design with a form factor
      between 0.5 an 2.
    - The tree is created at the block top-level and only the leafs are
      trans-hierarchically created on the instances/models. The new
      cell with a clock tree, along with all it's sub-models is created
      with a "_clocked" suffix.
    - Leaf cells are connected through a simple Minimum Steiner Tree.
    - Shorts are avoided by a systematic shift of the wires according
      to their kind. No wire must pre-exist. When used as a sub-module
      of "chip" the wires cannot be moved. When created on a block,
      the wires can be loaded in the detailed router as manual global
      router.
    Chip Plugin:
    - Perform the pad placement and corona creation. Replacement at
      last of the clunky code from Wu Yifei.
    - Relies on a Python configuration file '<design>_chip.py' with
      a "chip" dictionnary.
2014-08-15 19:05:27 +02:00
..
cmake_modules * ./crlcore: 2013-03-13 13:38:38 +00:00
doc Correction of SoC.css, adjust the look of the class index big letters. 2014-06-10 00:04:48 +02:00
etc Added support for MOSIS 180nm SCMOS technology (SCN6M_DEEP). 2014-08-03 16:36:21 +02:00
src First basic version of ClockTree & Chip plugins. 2014-08-15 19:05:27 +02:00
CMakeLists.txt Starting to implement support for Windows/Cygwin. 2014-07-13 13:14:49 +02:00