lanserge 44ce8dd162 Added Verilog driver for netlist export (#80) ... CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>		2023-11-02 14:09:33 +00:00
..
LibraryManager	Add support for building with Meson	2023-10-06 16:50:35 +01:00
ccore	Added Verilog driver for netlist export (#80)	2023-11-02 14:09:33 +00:00
cyclop	Add support for building with Meson	2023-10-06 16:50:35 +01:00
fonts	* ./hurricane/src/hviewer,	2010-03-09 15:20:13 +00:00
pyCRL	Added Verilog driver for netlist export (#80)	2023-11-02 14:09:33 +00:00
x2y	Add a flag througout all the build system to manage manylinux (PyPI).	2023-07-03 19:54:01 +02:00
CMakeLists.txt	Only build cycop and x2y when in debug build	2023-02-21 16:10:55 +01:00