CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io> |
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.. | ||
LibraryManager | ||
ccore | ||
cyclop | ||
fonts | ||
pyCRL | ||
x2y | ||
CMakeLists.txt |
CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io> |
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---|---|---|
.. | ||
LibraryManager | ||
ccore | ||
cyclop | ||
fonts | ||
pyCRL | ||
x2y | ||
CMakeLists.txt |