139 lines
6.7 KiB
Python
139 lines
6.7 KiB
Python
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# This file is part of the Coriolis Software.
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# Copyright (c) UPMC 2019-2019, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | Alliance / Hurricane Interface |
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# | |
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# | Author : Jean-Paul CHAPUT |
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# | E-mail : Jean-Paul.Chaput@lip6.fr |
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# | =============================================================== |
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# | Python : "./node600/phenitec/devices.py" |
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# +-----------------------------------------------------------------+
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import helpers.io
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helpers.io.vprint( 2, ' - "%s".' % helpers.truncPath(__file__) )
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import common.devices
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from common.devices import addDevice
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chamsDir = helpers.sysConfDir + '/share/coriolis2/'
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spiceDir = chamsDir + 'spice/'
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addDevice( name = 'DifferentialPairBulkConnected'
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, spice = spiceDir+'DiffPairBulkConnected.spi'
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, connectors = ( 'D1', 'D2', 'G1', 'G2', 'S' )
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, layouts = ( ('Horizontal M2' , 'DP_horizontalM2.py' )
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, ('Symmetrical' , 'DP_symmetrical.py' )
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, ('Common centroid', 'DP_2DCommonCentroid.py')
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, ('Interdigitated' , 'DP_interdigitated.py' )
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, ('WIP DP' , 'WIP_DP.py' )
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)
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)
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addDevice( name = 'DifferentialPairBulkUnconnected'
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, spice = spiceDir+'DiffPairBulkUnconnected.spi'
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, connectors = ( 'D1', 'D2', 'G1', 'G2', 'S', 'B' )
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, layouts = ( ('Horizontal M2' , 'DP_horizontalM2.py' )
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, ('Symmetrical' , 'DP_symmetrical.py' )
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, ('Common centroid', 'DP_2DCommonCentroid.py')
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, ('Interdigitated' , 'DP_interdigitated.py' )
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, ('WIP DP' , 'WIP_DP.py' )
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)
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)
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addDevice( name = 'LevelShifterBulkUnconnected'
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, spice = spiceDir+'LevelShifterBulkUnconnected.spi'
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, connectors = ( 'D1', 'D2', 'S1', 'S2', 'B' )
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, layouts = ( ('Horizontal M2' , 'LS_horizontalM2.py' )
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, ('Symmetrical' , 'LS_symmetrical.py' )
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, ('Common centroid', 'LS_2DCommonCentroid.py')
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, ('Interdigitated' , 'LS_interdigitated.py' )
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)
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)
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addDevice( name = 'TransistorBulkConnected'
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, spice = spiceDir+'TransistorBulkConnected.spi'
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, connectors = ( 'D', 'G', 'S' )
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, layouts = ( ('Rotate transistor', 'Transistor_rotate.py')
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, ('Common transistor', 'Transistor_common.py')
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, ('WIP Transistor' , 'WIP_Transistor.py' )
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)
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)
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addDevice( name = 'TransistorBulkUnconnected'
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, spice = spiceDir+'TransistorBulkUnconnected.spi'
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, connectors = ( 'D', 'G', 'S', 'B' )
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, layouts = ( ('Rotate transistor', 'Transistor_rotate.py')
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, ('Common transistor', 'Transistor_common.py')
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, ('WIP Transistor' , 'WIP_Transistor.py' )
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)
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)
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addDevice( name = 'CrossCoupledPairBulkConnected'
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, spice = spiceDir+'CCPairBulkConnected.spi'
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, connectors = ( 'D1', 'D2', 'S' )
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, layouts = ( ('Horizontal M2' , 'CCP_horizontalM2.py' )
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, ('Symmetrical' , 'CCP_symmetrical.py' )
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, ('Common centroid', 'CCP_2DCommonCentroid.py')
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, ('Interdigitated' , 'CCP_interdigitated.py' )
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)
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)
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addDevice( name = 'CrossCoupledPairBulkUnconnected'
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, spice = spiceDir+'CCPairBulkUnconnected.spi'
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, connectors = ( 'D1', 'D2', 'S', 'B' )
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, layouts = ( ('Horizontal M2' , 'CCP_horizontalM2.py' )
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, ('Symmetrical' , 'CCP_symmetrical.py' )
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, ('Common centroid', 'CCP_2DCommonCentroid.py')
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, ('Interdigitated' , 'CCP_interdigitated.py' )
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)
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)
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addDevice( name = 'CommonSourcePairBulkConnected'
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, spice = spiceDir+'CommonSourcePairBulkConnected.spi'
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, connectors = ( 'D1', 'D2', 'S', 'G' )
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, layouts = ( ('Horizontal M2' , 'CSP_horizontalM2.py' )
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, ('Symmetrical' , 'CSP_symmetrical.py' )
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, ('Interdigitated' , 'CSP_interdigitated.py' )
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, ('WIP CSP' , 'WIP_CSP.py' )
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)
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)
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addDevice( name = 'CommonSourcePairBulkUnconnected'
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, spice = spiceDir+'CommonSourcePairBulkUnconnected.spi'
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, connectors = ( 'D1', 'D2', 'S', 'G', 'B' )
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, layouts = ( ('Horizontal M2' , 'CSP_horizontalM2.py' )
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, ('Symmetrical' , 'CSP_symmetrical.py' )
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, ('Interdigitated' , 'CSP_interdigitated.py' )
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, ('WIP CSP' , 'WIP_CSP.py' )
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)
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)
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addDevice( name = 'SimpleCurrentMirrorBulkConnected'
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, spice = spiceDir+'CurrMirBulkConnected.spi'
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, connectors = ( 'D1', 'D2', 'S' )
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, layouts = ( ('Horizontal M2' , 'SCM_horizontalM2.py' )
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, ('Symmetrical' , 'SCM_symmetrical.py' )
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, ('Common centroid', 'SCM_2DCommonCentroid.py')
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, ('Interdigitated' , 'SCM_interdigitated.py' )
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)
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)
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addDevice( name = 'SimpleCurrentMirrorBulkUnconnected'
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, spice = spiceDir+'CurrMirBulkUnconnected.spi'
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, connectors = ( 'D1', 'D2', 'S', 'B' )
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, layouts = ( ('Horizontal M2' , 'SCM_horizontalM2.py' )
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, ('Symmetrical' , 'SCM_symmetrical.py' )
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, ('Common centroid', 'SCM_2DCommonCentroid.py')
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, ('Interdigitated' , 'SCM_interdigitated.py' )
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)
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)
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addDevice( name = 'MultiCapacitor'
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#, spice = spiceDir+'MIM_OneCapacitor.spi'
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#, connectors = ( 'T1', 'B1' )
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, layouts = ( ('Matrix', 'CapacitorMatrix.py' ),
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)
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)
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addDevice( name = 'Resistor'
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#, spice = spiceDir+'MIM_OneCapacitor.spi'
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, connectors = ( 'PIN1', 'PIN2' )
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, layouts = ( ('Snake', 'ResistorSnake.py' ),
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)
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)
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