riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity
coriolis/crlcore
History
Jean-Paul Chaput bf0d1ef350 More accurate layout detection in CRL::GdsDriver. 
* Bug: In CRL::GdsDriver::hasLayout(), a Cell was saved in the GDSII
    stream only if it has a layout, but the check was not accurate
    enough. In the Arlet6502, the whole core was missing.
      Now check for the abscence of Plugs (not unfinished Nets) and
    PLACED/FIXED instances.
 		2020-11-14 18:48:49 +01:00
..
cmake_modules Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
doc Documentation cleanup & rebuild. 2020-11-12 14:22:31 +01:00
etc Update cmos45 for use with FlexLib I/O symbolic abstracts. 2020-11-02 17:18:40 +01:00
python Update cmos45 for use with FlexLib I/O symbolic abstracts. 2020-11-02 17:18:40 +01:00
src More accurate layout detection in CRL::GdsDriver. 2020-11-14 18:48:49 +01:00
CMakeLists.txt Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00