coriolis/crlcore
Jean-Paul Chaput 1babec2e91 Save VHDL model only once in the rsave Cumulus plugin.
* Bug: In cumulus/plugins/rsave.py, the Cells where saveds each time
    one instance of was encountered. Resulting in multiple saves.
    It was, of course, ineficient, but it also triggers a bug
    that seems to happen after multiple save : the VHDL additional
    property was deleted *before* the full hierarchical dump was
    finished.
      Now, we save each Cell only once so it does not occur, but
    should make a deeper investigation later.
2022-05-21 13:02:58 +02:00
..
cmake_modules include/coriolis -> include/coriolis2 2021-08-27 16:15:28 +00:00
doc Update documentation (by mistake, nothing new). 2021-11-21 23:40:40 +01:00
etc Set the a default pixel threshold in CRL/etc/commons.display. 2021-11-26 11:32:33 +01:00
python Adapt Nix code to Python 3 switch. 2021-10-26 20:10:59 +00:00
src Save VHDL model only once in the rsave Cumulus plugin. 2022-05-21 13:02:58 +02:00
CMakeLists.txt Fix library linking problem for gcc 9 and above (Ubuntu 20/Debian 11). 2021-11-22 00:05:48 +01:00