lanserge 44ce8dd162 Added Verilog driver for netlist export (#80) ... CRL.Verilog.save(cell, 0) -> exports cell into Verilog netlist file Co-authored-by: Serge Rabyking <serge.rabyking@chipflow.io>		2023-11-02 14:09:33 +00:00
..
cmake_modules	include/coriolis -> include/coriolis2	2021-08-27 16:15:28 +00:00
doc	Build doc pelican (#11)	2023-08-01 15:43:21 +02:00
python	In BlockConf.useHTree(), must set the useClockTree flag (for chip mode).	2023-10-20 10:52:58 +02:00
src	Added Verilog driver for netlist export (#80)	2023-11-02 14:09:33 +00:00
CMakeLists.txt	Do not try to install the doc when not generated.	2023-08-04 15:37:08 +02:00
meson.build	Add support for building with Meson	2023-10-06 16:50:35 +01:00