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coriolis/crlcore
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Jean-Paul Chaput 09192ba084 Bug fix, check for unconnected signals in CRL::VectorPortMap::toVhdlportMap(). 
* Bug: In CRL::VectorPortmap::toVhdlPortMap(), unconnected bits where
    correctly checkeds for multi-bits vectors (both ordered and holed),
    but not for mono-bits connections (ONE bit of a vector).
 		2020-06-09 14:08:08 +02:00
..
cmake_modules Compliance with Debian 10 Buster. 2020-03-19 18:18:35 +01:00
doc Full update of the generated documentation. 2020-04-27 14:14:03 +02:00
etc Bug fix, restore the FreePDK 45 (real) support. 2020-04-27 10:34:19 +02:00
python More PEP8 compliant Python code. Start rewrite Python/C++ wrappers. 2020-04-08 11:24:42 +02:00
src Bug fix, check for unconnected signals in CRL::VectorPortMap::toVhdlportMap(). 2020-06-09 14:08:08 +02:00
CMakeLists.txt Groudwork for routing density driven placement. Compliance with clang 5.0.1. 2019-12-09 01:57:44 +01:00