Commit Graph

237 Commits

Author SHA1 Message Date
Jean-Paul Chaput 2c73cfe76c Migrating the initialisation system to be completely Python-like.
* New: In bootstrap/coriolisEnv.py, add the "etc" directory to the
    PYTHONPATH as initialization are now Python modules.
* New: In Hurricane/analogic, first groundwork for the integration of
    PIP/MIM/MOM multi-capacitors. Add C++ and Python interface for the
    allocation matrix and the list of capacities values.
* Change: In Hurricane::RegularLayer, add a layer parameter to the
    constructor so the association between the RegularLayer and it's
    BasicLayer can readily be done.
* Change: In Hurricane::Layer, add a new getCut() accessor to get the
    cut layer in ViaLayer.
* Change: In Hurricane::DataBase::get(), the Python wrapper should no
    longer consider an error if the data-base has not been created yet.
    Just return None.
* Bug: In Isobar::PyLayer::getEnclosure() wrapper, if the overall
    enclosure is requested, pass the right parameter to the C++ function.
* Change: In AllianceFramework, make public _bindLibraries() and export
    it to the Python interface.
* Change: In AllianceFramework::create(), do not longer call bindLibraries().
    This now must be done explicitely and afterwards.
* Change: In AllianceFramework::createLibrary() and
    Environement::addSYSTEM_LIBRARY(), minor bug corrections that I don't
    recall.
* Change: In SearchPath::prepend(), set the selected index to zero and
    return it.
* Change: In CRL::System CTOR, add "etc" to the PYTHONPATH as the
    configuration files are now organized as Python modules.
* New: In PyCRL, export the CRL::System singleton, it's creation is no
    longer triggered by the one of AllianceFramework.
* New: In CRL/etc/, convert most of the configuration files into the
    Python module format. For now, keep the old ".conf", but that are no
    longer used.
      For the real technologies, we cannot keep the directory name as
    "180" or "45" as it not allowed by Python syntax, so we create "node180"
    or "node45" instead.
      Most of the helpers and coriolisInit.py are no longer used now.
    To be removed in future commits after being sure that everything
    works...
* Bug: In AutoSegment::makeDogleg(AutoContact*), the layer of the contacts
    where badly computed when one end of the original segment was attached
    to a non-preferred direction segment (mostly on terminal contacts).
      Now use the new AutoContact::updateLayer() method.
* Bug: In Dijkstra::load(), limit symetric search area only if the net
    is a symmetric one !
* Change: In Katana/python/katanaInit.py, comply with the new initialisation
    scheme.
* Change: In Unicorn/cgt.py, comply to the new inititalization scheme.
* Change: In cumulus various Python scripts remove the call to
    helpers.staticInitialization() as they are not needed now (we run in
    only *one* interpreter, so we correctly share all init).
      In plugins/__init__.py, read the new NDA directory variable.
* Bug: In cumulus/plugins/Chip.doCoronafloorplan(), self.railsNb was not
    correctly managed when there was no clock.
* Change: In cumulus/plugins/Configuration.coronaContactArray(), compute
    the viaPitch from the technology instead of the hard-coded 4.0 lambdas.
      In Configuration.loadConfiguration(), read the "ioring.py" from
    the new user's settings module.
* Bug: In stratus.dpgen_ADSB2F, gives coordinates translated into DbU to
    the XY functions.
      In st_model.Save(), use the VstUseConcat flag to get correct VST files.
      In st_net.hur_net(), when a net is POWER/GROUND or CLOCK also make it
    global.
* Change: In Oroshi/python/WIP_Transistor.py, encapsulate the generator
    inside a try/except block to get prettier error (and stop at the first).
2019-10-28 18:09:14 +01:00
Jean-Paul Chaput 1da71ae740 Bug when the METAL3 pitch is not multiple of METAL1.
* Bug: In Katana::SegmentFsm CTOR, when computing costs for METAL2 in
    non-preferred direction attached to METAL1 terminals, do not try to
    align on a METAL3 track, as there may be not. Especially when the
    METAL3 pitch is not multiple of the METAL1 one.
      Compute at least one cost (with the same axis as the vertical METAL1
    terminal).
* Change: In Etesian::BloatCells, adjust the "90%" bloat profile for a
    METAL3 pitch of 8 lambdas (sligh decrease).
* Bug: In cumulus/plugins/ChipPLace.py, import chip.Chip, not only chip.
2019-10-16 21:47:32 +02:00
Jean-Paul Chaput 5bbeb0b062 Support for separated NDA tree. Big cleanup of the Python init system.
* Change: In Hurricane::Script, when running a script, no longer do it
    inside a Python sun-interpreter, use the current one. This way we
    no longer have our modules initialized twice or more, which was
    starting to be unmanageable (with the NDA support).
      The settings were re-read multiple time to the same value, so it
    was working, but still...
      I hope I didn't left some dangling Python objects now.
* Bug: In Hurricane::LayoutGenerator::drawLayout(), get the device abutment
    box though a Pyhon object *before* finalizing which removes that objet.
* New: In cumulus/plugins/__init__.py, add a "loadPlugins()" and static
    initialisation to preload plugins modules.
      We use that pre-loading step to append to the module __path__ attribute
    the alternate directory where a NDA covered may be found. This assume that
    the directory tree under the NDA root is identical to the one under the
    public root.
* New: In cumulus/plugins/chip/__init__.py, small utility function
    importContants() to import the constants inside another module namespace,
    to have more consise notations.
* Change: In cumulus/plugins/, in the various plugins sub-modules import
    use the full path from plugins, that is, for example:
      from plugins.core2chip.CoreToChip import IoPad
* Change: In Unicorn/python/unicornInit.py, no longer directly load the
    plugins modules, this is now done by cumulus/plugins/__init__.py.
      Instead, iterate through sys.modules for the ones starting by "plugins/"
    and try to execute a Unicorn hook, if present.
* Change: In Karakaze/python/AnalogDesign.py, update for the new Instance.create()
    prototype (added placement parameter).
2019-10-11 17:36:54 +02:00
Jean-Paul Chaput 5914e16f26 Added management for "phlib" I/O pad external connectors (for cougar/lvx).
* New: In CRL::ApDriver::DumpSegments(), drive as top-level segments the
    RoutingPads using a Pin, and not only using a segment. They are not
    exported as top level Pin but only as Segment as they do belong to
    a deeper level.
* New: In Cumulus/plugins/PadsCorona.Side._placePads(), now manage both
    "pxlib" and "phlib*". Pad library management is still hardcoded, this
    should be made a configuration option someday.
2019-10-05 16:04:12 +02:00
Jean-Paul Chaput 2bd18313d1 More tuning for ARMv2a (95% success, 38/40). Bugs in core2chip.
* Change: In Anabatic::GCell::updateDensity(), all non-passthrough wires
    now have a cost of 0.5 instead of 0.33 for locals.
* Change: In Manipulator::canMoveUp(), increase the "reserve" amount to
    1.0 for "far from terminal" wires (rpDistance > 2).
* Change: In NegociateWindow::NegociateOverlapCost(), always sets "AtRipupLimit"
    when the overlapping segment is nearing it's maximum ripup limit.
    (different detection for non-preferred and regular)
* Change: In SegmentFsm::_slackenStrap(), call avoidBlockage() if it is
    overlapping a blockage *or* a segment at it's ripup limit. I hope I
    didn't create an infinite loop here.
* Bug: In cumulus/plugins/PadsCorona.py, CoreWire._computeCoreLayers(),
    the big contact between symbolic and real was badly computed for
    east/west (was using width instead of height, bummer!).
      In Corona._createCoreWire(), completly screwed computation of the
    side gap, was using a badly initialized value of the "bb" variable.
* Bug: In cumulus/plugins/Chip.py, the computation of the minimal size
    for the corona was wrong, do *not* add the size of the pads and
    multiply by two as it is done by "inflate". This was forcing the user
    to create way to large chips for a given core size.
2019-09-25 18:35:03 +02:00
Jean-Paul Chaput 24dedce09c Added core2chip support for Phenitec80.
This commit degrades the run success rate of ARMv2a to 87% (40 iters).
* New: In CRLcore/etc/.../kite.conf, add configuration parameters:
      katana.termSatReservedlocal
      katana.termSatthreshold
    for the new edge capacity computation system.
* New: In CRLcore/etc/symbolic/phenitec06/, add support for N. Shimizu
    small I/O pads (supplied in phlib80). Tune various parameters of
    Anabatic/Katana to increase routing success.
* Change: In CRLcore/alliance/ap/ApParser, make Pin external components,
    so RoutingPad will be build upon in global routing.
      Do not complain when a I/O pad has a physical instance that did
    not exists in the netlist. Just create it (appeared in phlib80).
      When no netlist instance exists in a pad, the pad Cell is still
    considered as terminal.
* New: In Etesian::BloatCells, new profile named "3metals" better suited
    for two routing metals technologies (i.e. Phenitec).
* New: In Anabatic::RawGCellsUnder, new CTOR which take only source &
    target points instead of a segment. Needed to manage wide segment for
    which the axis to consider is not that of the segment (one axis for
    each track it intersect).
* New: In Anabatic::GCell, add a RoutingPad count attribute, for Edge
    reservation computation.
* New: In AnabaticEngine::computeEdgeCapacities(), instead of decreasing
    all edges of a fixed amount (hTrackReservedLocal), guess the GCell
    cluttering from the number of RoutingPads that it contains.
      For non-saturated GCells, the four edges are decreased by the number
    of RoutingPads. We use the maximum from the two neigboring GCells.
    The hTrackReservedLocal parameter is now used only as a *maximum*
    that the edge reservation can reach.
      If a GCell is saturated (more than 8 RoutingPads, the saturation is
    propagated horizontally to 2 neigboring GCells).
* Change: In AutoContactTerminal::getNativeConstraintBox(), use a more
    flexible gauge name matching for terminal vertical extensions correction.
    Namely, match all "msxlib*" kind of gauges.
* Change: In AutoSegment::setAxis(), add the ability to force the axis
    position, even if it is a non-canonical segment. Maybe needed in the
    initialisation steo, before the first canonisation is performed.
* New: In NetBuilder, added new methods _do_1G_1PinM1() and _do_2G_1PinM1(),
    to manage coronas for Phenitec designs.
      To avoid various side effects from segments being too close from
    the north / east side of the routing area, make those segments fixeds.
* Change: In KatanaEngine::annotateGlobalGraph(), the management of wide
    wires was wrong. The axis to use to find the underlying GCells is the
    one of the track, not of the segment. This was creating bad edge
    capacity computation under the power ring of a block and subsequently
    routing failures.
* New: In Kanata::Manipulator, added method reprocessParallels(), not used
    though, but keep it anyway, might be of use later...
* New: In Kanata::Manipulator, added method avoidBlockage() for terminal
    METAL2 in non-preferred direction, restrict the terminal and turn
    constraint box at the current position of the perpandicular, so it
    doesn't create a deadlock in METAL2.
* Change: In SegmentFsm::conflictSolveByPlaceds(), if we cannot break
    using the whole overlap, try the first atomic overlap.
* New: In SegmentFsm::_slackenStrap(), manage conflict between a non-prefered
    segment and a blockage, this when to call avoidBlockage()...
* New: In Katana::Configuration, management of the new edge computation
    parameters:
      katana.termSatReservedlocal
      katana.termSatthreshold
* New: In Cumulus/plugins/Core2Chip, support for Phenitec I/O pads.
2019-09-17 17:05:54 +02:00
Jean-Paul Chaput 91f973c00f Improve the management of the I/O pad near the chip corner.
* Bug: In cumulus/plugins/PadsCorona.py, when a pad is at the beginning
    or at the end of the side, the pad corona terminal may be outside
    the corona range (not directly facing it). In that case, create a
    bend to reach it.
      Worse, in some case more than one (but likely no more), could be
    in that case, so not only do we create a bend but also make a
    shift in the bended segment so two consecutive ones are not on the
    same axis, causing shorts.
      If both end pads of a corner are in that case, we cannot prevent
    a short, so at least, issue a warning.
* Bug: In CRL::Vhdl, the Entity::VstUseConcat was not passed correctly
    along, so we did get a strange mix of conat and direct assignment.
* New: In Unicorn/cgt.py : added --vst-use-concat options to control
    the VST driver behavior.
2019-08-16 00:40:49 +02:00
Jean-Paul Chaput d670de4125 Added support for 3 metal layers symbolic Phenitec 0.6um.
* New: In CRL/etc/symbolic/phenitec06, configuration for symbolic
    layout targeted for Phenitec 0.6um (do not contains any NDA
    covered informations). Could be used for any 3 metal layers
    techno.
* Bug: In Cumulus/plugins/chip/Configuaration.py, _setStackposition()
    disable stack error when there is no slave component on the stack
    (happens when the stack consists only of one contact).
2019-08-12 15:41:17 +02:00
Jean-Paul Chaput 4b9a6ec4a9 Ensure that there is at least one free GCell on each side of the corona.
* Change: In Cumulus/plugins/chip/PadsCorona, if the external pins of
    the corona are in GCells that are also under the core block ring
    power lines, they are flagged as "go straight" and this produce
    impossible configurations for the router to solve. Now we ensure
    that there is one free GCell all around the corona border.
* Bug: In Cumulus/plugins/chip/Configuration.py & PadsCorona.py,
    at the begin/end of a side of pad, connectors can be outside the
    corona range (i.e. not directly face to face). Now make a dogleg
    if needed. This is a work in progress as if there are two of them,
    they will short on the perpandicular part. We must compute a
    shift.
2019-08-12 01:11:58 +02:00
Jean-Paul Chaput 70a3960ba5 ioNet used as "enable" should not get the name of the pad.
* Bug: In Cumulus/plugins/core2chip/CoreToChip.py, when creating the ioNet
    objects, when a signal is an enable we must not set the external chip
    net (the name for the PAD terminal) as it may be set later if it is
    also used as an individual pad.
2019-08-09 18:45:19 +02:00
Jean-Paul Chaput 15cd9187de Allow enable signal of bidir pads to be exported in Core2Chip.
* Change: In Cumulus/plugins/core2chip/CoreToChip.py, in IoNet select
    the external I/O net (pad connected) signal to be generated in the
    context of the I/O pad instanciation. This should allow an enable
    signal in one pad to be also used in a direct output pad.
2019-08-09 12:56:54 +02:00
Jean-Paul Chaput 86c4e9cb17 Added support for Tristate and bidir pads in CoreToChip.
* New: In Cumulus/plugins/CoreToChip, added support for Tristate ouput
    pads and bidirectional pads.
      Added capability to name the I/O pad instance and their external
    terminals so we can override the default naming scheme.
      Mandatory anyway for bidirectional and tristate I/O pad as we
    cannot guess the core net grouping (in/out/enable).
      Support is available for symbolic CMOS and AMS c35b4 (but not
    published due to NDA).
* Change: In Cumulus/plugins/chip/Configuration.py, the configuration
    file is now named simply "ioring.py" instead of being prefixed by
    the design name. As a consequence we can have only one chip per
    directory. But now all the tools, for any design in that directory
    can peek datas into it.
2019-08-08 00:57:19 +02:00
Jean-Paul Chaput acc3a38f60 Support for placing *one* block of a Cell in Etesian.
* Change: In Hurricane::Cell_LeafInstanceOccurrences, add the ability to
    walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell_NonLeafInstanceOccurrences, add the ability to
    walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell:
    getLeafInstanceOccurrences() and getNonLeafInstanceOccurrences(), now
    have a parameter Instance* to select the leafs we want to walk through.
    If set NULL (default value) browse through all the instances,
    as before.
* Change: In Hurricane::DeepNet, add forgotten Inspector support.
* New: In EtesianEngine, add a "block" (and Instance) attribute to allow
    the placement of one specific bloc. If we want to place the core of
    a chip and take into account the external terminals (if they are not
    already fixed as Pins at the edge of *said* block). We must place
    the core *in the context* of it's instanciation in the corona.
      Note for G. Gouvine : Pin & external RP should be taken into account
    starting at line 629 of EtesianEngine.cpp...
* New: In cumulus/plugins/chip/Chip.py, make use of the new block
    placement feature of ETesian.
* Bug: In KatanaEngine::create(), perform a pre-check to prevent trying to
    route whole chip, which is forbidden an leads to annoying core-dumps.
    Routing must take place "at most" at Corona level.
* Bug: In KatanaEngine::PowerRails, create a plane for METAL1 blockage.
    Not completely sure this was a bug...
2019-08-04 17:33:03 +02:00
Jean-Paul Chaput 1b444d8f49 In cumulus/Core2Chip.py forgot a parameter to an error message call. 2019-07-31 19:16:40 +02:00
Jean-Paul Chaput d69327d9a9 Various typos correction (courtesy of G. Gouvine). 2019-07-30 13:13:57 +02:00
Jean-Paul Chaput f528cdea4c Upgrade of Katana detailed router to support Arlet 6502.
* Change: In Hurricane::SharedName, replace the incremental Id by a hash key.
    This is to ensure better deterministic properties. Between use cases,
    additional strings may have to be allocated, shitfing the ids. Even if
    hash can be duplicated, we should be able to ensure that the absolute
    order in map table should be preserved. Supplemental strings are inserted
    in a way that keep the previous order.
* Change: In CRL/etc/symbolic/cmos/kite.conf, add "katabatic.routingGauge"
    default parameter value ("sxlib").
* Change: In CRL/etc/common/technology.conf, define minimal spacing for
    symbolic layers too (added for METAL4 only for now).
* Change: In CRL::Histogram, extend support to dynamically sized histograms.
    Add a text pretty print with table and pseudo-curve.
* Change: In Cumulus/plugins/ClockTreePlugin, create blockage under the
    block corona corners so the global router do not draw wire under them.
    This was creating deadlock for the detailed router.
      When the abutment has to be computed, directly use Etesian to do it
    instead of duplicating the computation in the Python plugin.
* New: In Etesian, as Coloquinte seems reluctant to evenly spread the
    standard cells, we trick it by making them bigger during the placement
    stage. Furthermore, we do not not uniformely increase the size of the
    cells but create a "bloating profile" based on cell size, cell name
    or it's density of terminals. Currently only two profiles are defined,
    "disabled" which does nothing and "nsxlib" targeted on 4 metal layer
    technologies (aka AMS 350nm, c35b4).
* Bug: In Knik::MatrixVertex, load the default routing gauge using the
    configuration parameter "katabatic.routingGauge" as the default one
    may not be the first registered one.
* New: In AnabaticEngine::setupNetDatas(), build a dynamic historgram of
    the nets terminal numbers.
* Bug: In Anabatic::AutoContact::Invalidate(), always invalidate the
    contact cache when topology is invalidated. In case of multiple
    invalidations, if the first did not invalidate the cache, later one
    that may need it where not allowed to do so. The end result was correct
    nonetheless, but it did generate annoying error messages.
* Bug: In Anabatic::AutoContactTurn::updateTopology(), bad computation
    of the contact's depth when delta == 2.
* Bug: In Anabatic::Gcell::getCapacity(), was always returning the west
    edge capacity, even for the westermost GCell, should be the east
    edge in that case.
* New: In Anabatic::AutoSegment, introduce a new measure "distance to
    terminal". This is the minimal number of segments separating the
    current one from the nearest RoutingPad. This replace the previous
    "strong terminal" and "weak terminal" flags.
      This distance is used by Katana to sort the events, we route the
    segments *from* the RoutingPads *outward*. The idea being that if we
    cannot event connect to the RoutingPad, there is no points continuing
    as thoses segments are the more constraineds. This gives an order close
    to the simple ascending metals but with better results.
* New: In Anabatic::AutoSegment, introduce a new flag "Unbreakable", disable
    dogleg making on those segments. mainly intended for local segments
    directly connecteds to RoutingPads (distance == 0).
* New: In Anabatic::AutoSegment, more aggressive reducing of segments.
    Now the only case where a segment cannot be reduced is when it is
    one horizontal branch in a HTee or a vertical on a VTee. Check if,
    when not accounted the source & target VIAs are still connex, if so,
    allow reducing.
* New: In Anabatic::AutoContact, new state flags CntVDogleg & CntHDogleg
    mainly to prevent making doglegs twice on a turn contact. This is to
    limit over-fragmentation. If one dogleg doesn't solve the problem,
    making a second one will make things worse only...
* Bug: In Anabatic::Configuration::selectRpcomponent(), we were choosing
    the component with the *smallest* span instead of the *bigger* one.
* New: In Anabatic::GCell, introduce a new flag "GoStraight" to tell that
    no turn go be made inside those GCells. Mainly used underneath a block
    corona.
* New: In AnabaticEngine::layerAssign(), new GCellRps & RpsInRow to manage
    GCells with too many terminals. Slacken at least one RoutingPad access
    when there is more than 8 RoutingPad in the GCell (slacken or change
    a vertical METAL2 (non-preferred) into a METAL3).
* Change: In Anabatic::NetBuilderHV, allow the use of terminal connection
    in non-preferred direction. That is, vertical METAL2 directly connected
    to the RoutingPad (then a horizontal METAL2). This alllows for short
    dogleg without clutering the METAL3 layer (critical for AMS c35b4).
      Done in NetBuilderHV::doRp_Access(), with a new UseNonPref flag.
      Perform some other tweaking on METAL1 access topologies, to also
    minimize METAL3 use.
* New: In AnabaticEngine::computeNetConstraints(), also compute the
    distance to RoutingPad for segments. Set the Unbreakable flag, based
    on the distance and segment length (local, short global or long global).
      New local function "propagateDistanceFromRp()".
* Change: In AnabaticEngine.h, the sorting class for NetData, SparsityOrder,
    is modificated so net with a degree superior to 10 are sorted first,
    whatever their sparsity. This is to work in tandem with GlobalRouting.
* New: In Katana::TrackSegmentNonPref, introduce a class to manage segment
    in non-preferred routing direction. Mostly intended for small METAL2
    vertical directly connected to RoutingPad. Modifications to manage
    this new variant all through Katana.
* Change: In Katana::GlobalRoute, DigitalDistance honor the GoStraight flag
    of the GCell. Do not make bend inside thoses GCells.
* Change: In KatanaEngine::runGlobalRouter(), high degree nets (>= 10) are
    routed first and whitout the global routing estimation. There should be
    few of them so they wont create saturations and we want them as straight
    as possible. Detour are for long be-points.
      Set the saerch halo to one GCell in the initial routing stage (before
    ripup).
* Bug: In KatanaEngine & NegociateWindow, call _computeCagedconstraints()
    inside NegociateWindow::run(), as segments are inserted into tracks
    only at that point so we cannot make the computation earlier.
* Change: In Katana::Manipulator::repackPerpandiculars(), add a flag to
    select whether to replace the perpandiculars *after* or *before* the
    current segment.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when the
    segment is fully enclosed inside a global, the longest overlap cost
    is set to the shortest global hoverhang (before or after).
      When the cost is for a global, set an infinite cost if the overlapping
    segment has a RP distance less or equal to 1 (this is an access segment).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), correct computation of
    the segments extension cap.
* New: In Katana::QueryPowerRails::addToPowerRail(), add support for Pad.
* Change: In Katana/PreProcess::protectCagedTerminals(), apply the contraints
    to any turn connected to the first segment of the RoutingPad so the
    perpandicular constraints got propagated to the perpandicular segment...
* Change: In RoutingEvent, cache the "distance to RP" value.
* Change: In RoutingEvent::Key::compare(), sort *first* on distance to
    RoutingPad, then layer depth. If both distance to RoutingPad is null,
    then sort on segment length.
* Change: In RoutingEvent::_processRepair(), try a repack perpandicular with
    perpandiculars first (then with perpandicular last, then give up).
* Change: In SegmentFsm::bindToTrack() and moveToTrack(), set an axis hint
    when creating the insertion event.
* Change: In SegmentFsm::_slackenStrap(), add a step through slacken between
    minimize and maximum slack (wihch directly end up in unimplemented).
* Change: In Session::_addInsertEvent(), add an axis parameter needed when
    the axis of the segment is not the one of the track (case of wide
    segments or non-preferred direction).
* Bug: In Track::_preDestroy(), bad management of the TrackElement reference
    count. Destroy the segment only when reaching zero...
* Bug: In Track::expandFreeIneterval(), forgotten to manage case when there
    is a set of overlaping segments at the "end" of the track, the
    EndIsTrackMax was not set.
* Change: In TrackCost::Compare, increase the cost when an overlaping
    segment is at it's ripup limit. We should try *not* to rip it up if
    we can. Add a dedicated flag "AtRipupLimit".
* Change: In TrackElement, add proxies for isUnbreakable(), new function
    updateTrackSpan().
* New: In TrackFixedSegment CTOR, when a supply wire of METAL2 or above is
    found, make the underlying GCells "GoStraight".
* New: In TrackElement::canDogleg(GCell*), check for already done perpandicular
    dogleg on source/target (reject if so).
2019-07-28 23:20:00 +02:00
Jean-Paul Chaput 4cd0bcb009 Various bug corrections to pass the alliance-check-toolkit reference benchs.
* New: In Isobar::PyCell, export the isRouted() and setRouted() to the
    Python interface.
* Bug: In CRL::Entity::parseEntity(), check that the closing parenthesis
    is the last character of the net name. Issue a more relevant error
    message.
* In Anabatic::NetBuilder::_do_xG() and all other unimplemented methods,
    throw an error if called from a derived classes instead of just
    issuing a message in the debug stream. Avoid later core dumps...
* In Anabatic::NetBuilderHV, implement the builders for GCells with
    one pin. Needed to support chip/corona routing.
* Bug: In Cumulus/plugins/Chip.py, check that coronaCk exists before
    using it.
* New: In Cumulus/plugins/PadsCorona/Side._placePad(), when routing
    a design with symbolic pads, export the chip external "pad"
    connectors to be able to perform a lvx (otherwise cougar do not
    create external nets).
      In Corona._createCoreWire(), set the minimal gap between the pads
    and the corona to 6 pitches. Empirical value to avoid DRC errors
    with symbolic pads (pxlib).
      When successufully done, mark the Corona cell as routed.
* Bug: In Cumulus/plugins/Core2Chip.IoNet, the regex for vectorizet net
    was wrong, it was allowing only one digit in the index.
* Bug: In Cumulus/plugins/Core2Chip.cmos, correct management of
    pad & corona clock nets. Correct connexion between vdde/vddi.
* Bug: In Unicorn/cgt.py, forgot to execute scripts when in text mode.
2019-05-24 23:57:22 +02:00
Jean-Paul Chaput 3fb746fbef Support for mixing real pads & symbolic core. Wrapper around s2r.
* Change: In Hurricane::Error constructors disable the backtrace generation.
    (*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
    naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
    More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
    to the state. This allow to load two cells with the same name but from
    different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
    CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
    table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
    along with a new ErrorWidget written in PyQt4. It seems finally that
    PyQt4 can be used alongside Coriolis Qt widgets.
      New ErrorMessage.catch() static function to manage all exceptions
    in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
    directly print it.
      Rewrite the utilities to display Python stack traces "textStacktrace()"
    and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
    Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
    longer made square but thin and oriented in the connecting direction.
      Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
    Due to the unordered nature of the GDS stream, instances creation are
    delayed until the whole stream has been parsed and only then are they
    created.
      For the sake of reading back Alliance s2r GDS, we assume that any
    TEXT following a boundary is the Net name the boundary (component)
    belongs to.
      Create abutment box for Cells, computed from the bounding box, so
    the Hurricane QuadTree could work properly.
      Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
    Now we can mix real (foundry) pads and a symbolic core.
      To cleanly support the de-coupling between the real part and the
    symbolic one we introduce a new intermediary hierarchical level, the
    corona. We have now:
      Chip --> Pads + Corona --> Core.
      At chip level (and if we are using real pads) the layout is fully
    real (excepting the corona).
      The Corona contains everything that is symbolic. It has symbolic
    wires extending outward the abutment box to make contact with the
    real wires coming from the pads.
      In the pad ring we can use corners instances (or not), pad spacers
    or directly draw wires between connectors ring pads.
      Provide two flavors: placement only or full place & route.
    WARNING: If routing in a second step, *do not route* the *Chip* but
    the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
    additional extension of "_cts" (Clock Tree Synthesis) instead of
    "_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
    reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
    create a chip from a core. To work this plugins must have a basic
    understanding of the pad functionalities which may differs from
    foundry to foundry. So a base class CoreToChip is created, then for
    each supported pad foundry a derived class is added. Currently we
    support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
    "anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
    to ensure a reproductible ordering of the menus...
2019-05-22 14:34:32 +02:00
Jean-Paul Chaput 82dc58bf8e Redesign of I/O pads and Corona support to mix real and symbolic.
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
    longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
    Must normalize Pin behavior between Alliance & Hurricane as in
    Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
    global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
    now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
    the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
    we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
    support:
    * Uncouple pad I/O ring whith real cells (foundry) from a symbolic
      core. A new intermediate level "corona" is introduced to handle
      the real/symbolic transition.
    * Ability to explicitly setup position of the pads on the chip side
      in case of uneven distribution.
    * Enable clock tree to be build with 3 metal only (M2 to M4) instead
      of (M2 to M5).
2019-05-10 11:58:05 +02:00
Jean-Paul Chaput 2beee8a25c Bug: Compopent creation inside a Collection loop In Cell::flattenNets().
* Bug: In Hurricane::Cell::flattenNets(): Same error again, do not create
    components while iterating over the components Collection.
      Now RoutingPad of top nets are create outside the loop as they must.
2019-05-10 11:48:33 +02:00
Jean-Paul Chaput 3a2916b5e6 Improved clock-tree support for variable pitch routing gauges.
* New: In Hurricane::Isobar::PySegment, added wrapper for getOppositeAnchor().
* Bug: CRL::PyRoutingLayerGauge, Python wrapper of getTrackPosition() was
    in fact returning getTrackNumer().
* Bug: In Katana::PowerRailsPlanes::Rail::doLayout(), add the half minimum
    distance to the blockage segments extensions. Was causing too near
    VIAs is cmos45.
* Change: In cumulus/plugins/ClockTree, correctly manage routing gauge when
    the lower pitches (M2/M3) is different from the upper one (M4/M5).
    But we still can only do sxlib compliant gauges because we do not
    handle a switch in preferred routing directions.
2019-03-23 11:05:51 +01:00
Jean-Paul Chaput f107a68938 Reorganisation of menus in a more clear way. 2019-03-05 23:23:14 +01:00
Jean-Paul Chaput 95aba574a5 Happy New Year 2018 ! Update license years... 2018-01-06 17:55:44 +01:00
Jean-Paul Chaput 2b9c929f80 Compliance with cmake 3.0 (Debian 9.2). Corrects all warnings. 2017-12-02 14:30:05 +01:00
Jean-Paul Chaput c339e5c9e3 Check for any version of Python 2, instead of 2.7. 2017-07-11 17:52:58 +02:00
Jean-Paul Chaput 8d4fdf3471 TrackCost clean support for symmetric and wide segments.
* New: In Katana::TrackCost, the TrackElement and it's optional
    symmetric are now kept as attribute of a TrackCost. The cost
    is completly computed inside the constructor.
      TrackCost now support any mix of symmetric event and wide
    segments.
      The cost is now computed by adding directly to the current
    one instead of creating secondaries that are merged afterwards.
    As a consequence, remove all copy construction and merge
    capabilities.
      All the various methods used to compute the cost are renamed
    "addOverlapcost()" in all the various related objects.
      As a reminder, the overal cost method call is as follow:
        1. TrackCost constructor on a TrackElement.
           2. Call TrackElement::addOverlapcost()
              3. For all Track under the TrackElement, call
                 Track::addOverlapCost()
                 4. For all other TrackElement intersecting with
                    the overlap interval call:
                    TrackElement::incOverlapCost()
                    5. The callback overlap function for segments
                       is called (defined in NegociateWidow).
      Don't confuse:
      - TrackElement::addOverlapCost(), which compute the cost of
          inserting the segment inside a track (or a set of).
      - TrackElement::incOverlapCost(), which compute the cost of
          overlaping with this already inserted segment. It is the
          other way around of the previous one.
* Change: In Katana::SegmentFsm, use a vector of pointer to TrackCost
    instead of an object to avoid copy construction.
2017-06-10 12:27:25 +02:00
Jean-Paul Chaput c44c6b13f3 Adjust Katana event sort. CMake detection of Python 2.7 only.
* Change: In all top CMakeLists.txt, force the use of Python 2.7 as
    we do not compile against 3.x flavors. Do not use the "EXACT"
    flags as it will not recognize 2.7.x versions.
* Change: In Katana::RoutingEvent::Key::Compare(), preliminary
    experiments shows that the best sorting order is:
      - Lower layer first (i.e. M2 -> M3 -> M4 -> ... )
      - Longer segments first.
      The later seems to be counter-intuitive. Guess is that placing
    the small ones first generate a more important fragmentation of
    the big ones. They are placed too early and are difficult to move
    afterwards.
      Another feature to test is *not* inserting pushed left/right
    segments if they are not *already* routed.
* Change: In PyKatanaEngine.runNegociate() now takes a flag argument,
    provided through the new PyKatanaFlags exported object.
    (doChip.py must be changed accordingly)
2017-05-11 17:26:56 +02:00
Jean-Paul Chaput d175e1b27a Correct way too slow clock-tree. Backport Katana fixes to Kite.
* Bug: In Hurricane::Net::setExternal(), do not perform an UpdateSession
    inside this function, it leads to unbearibly slow operation in the
    clock-tree plugin.
* Bug: In Kite, backport corrections done in Katana and also relevant
    for Kite.
* New: In Cumulus.ChipPlugin.py add support for Python profiling with
    cProfile. Disabled under normal operation, but will certainly come in
    handy sometimes.
2016-12-02 00:13:17 +01:00
Jean-Paul Chaput 5435ca1933 Added missing UpdateSession in Stratus & Plugins.
* Bug: In Cumulus & Stratus, now that creation of Hurricane objects must be
    enclosed in UpdateSession, has to adds them into Python code.
* Bug: In Anabatic & Katana, in the global routing stage suspend the timed
    bewteen ripup steps instead of resetting it.
2016-09-11 13:20:05 +02:00
Jean-Paul Chaput eed9cc6f91 Do not generate stacked VIAs twice in ClockTree plugin.
* Bug: In Cumulus, in ClockTree plugin in GaugeConf._rpAccess() do not
    create the stack of access VIAs each time the function is called.
    Instead maintain a lookup table of the already generated ones.
      Was blocking the loading of pre-routed nets in Anabatic.
2016-07-22 00:08:04 +02:00
Jean-Paul Chaput 8328c890bb In Stratus, in dpgen_RAM get cell height from the library.
* Change: In Stratus, in dpgen_RAM, the cell height was fixed to 50l.
    Now read the prech[0] to set up the cell height (useful for MOSIS
    cells).
* New: In Stratus, in buildModel(), the stand alone generator caller
    now support a className, a modelName and a set of parameters to
    pass on to the model. This is very useful when the module name
    (the file), the class name and the model name are not the same.
2016-04-13 18:49:50 +02:00
Jean-Paul Chaput d641f236a3 Suppress warnings when flatening a Cell twice.
* In Hurricane, in Cell::flattenedNets(), if the cell has already been
    flattened, do not issue warnings about duplictated flattened nets.
* In Hurricane, in Net, allow Net::setName() to switch the main name
    for an alias without complaining about an already used name.
* In Cumulus, in RSavePlugin.py, when "views" is supplied in keywords
    (kw) arguments, override the default instead of merging with it.
    This is to allow scripts to save exactly what views they want.
2016-04-02 14:47:10 +02:00
Jean-Paul Chaput 6ad644fac2 New relation for slaved ABs. Do *not* delete blockage nets.
* Change: In Hurricane, in DataBase::CellDepths() the recursion stop
    criterion must be Cell::isLeaf() and not Cell::isTerminal() as
    the second one can be used to hide some levels of hierarchy,
    and we want all of them in a blob.
* New: In Hurricane, in Cell, create a new Slaveds relation to keep
    track of all the Cells with a slaved abutment box. This work is
    incomplete as we do not manage the behavior in case of merge or
    Cell destruction or slaving Cells with aready slaveds ones.
      Modify Cell::setAbutmentBox() to work in both autonomous and
    slaved mode.
* New: In Hurricane, in Net, add a new type of Net: BLOCKAGE this
    avoid us to be dependant on the framework pattern recognition.
    (change propagated to the Python support)
* New: In CRL Core, in the various drivers, recognize blockage nets
    as such and set their type accordingly.
* Change: In CRL, in Toolbox::deleteEmptyNets(), preserve blockage
    Nets. This was the cause of crashs in Kite::BuildPowerRails() as
    we where trying to use a deleted blockage net...
* Bug: In Hurricane, in NetAlias, do not write NetAlias as a name
    but as a type. They were not read back and moreover staying in
    the JSON parser stack.
2016-03-30 17:47:00 +02:00
Jean-Paul Chaput a78882fd5b Clocks in BLIF parser. In RSavePlugin, flags to select views to save.
* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
    specify which views must be saved. Physical by default, but sometimes
    we need logical as well. If the design contains uniquified cells,
    save the logical view.
      In ClockTree, abort the clock tree building if the design has no
    top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
   composing the H-Tree must be protecteds be blockages.
2016-03-26 11:59:32 +01:00
Jean-Paul Chaput b2374c73b8 scmos_deep_018 switched to nsxlib. Minor bugs in plugins. 2016-03-10 17:05:36 +01:00
Jean-Paul Chaput 1b7bd9de36 Happy new year 2016! 2016-01-21 00:41:19 +01:00
Jean-Paul Chaput 7669c66597 In Cumulus/PadsCorona.py, now manage global nets explicitly connecteds. 2015-09-06 17:14:24 +02:00
Jean-Paul Chaput ed557d9027 Added support for "same layer" dogleg. Big fix for pad routing.
* Change: In Knik, in Vertex, add a "blocked" flag to signal disabled
    vertexes in the grid (must not be used by the global router).
      Modificate the Graph::getVertex() method so that when a vertex
    is geometrically queried, if is a blocked one, return a non-blocked
    neighbor. This mechanism is introduced to, at last, prevent the
    global router to go *under* the pad in case of a commplete chip.
* New: In Katabatic, in AutoSegment, a new state has been added: "reduced".
    A reduced segment is in the same layer as it's perpandiculars.
    To be reduced, a segments has to be connected on source & target to
    AutoContactTurn, both of the perpandiculars must be of the same layer
    (below or above) and it's length must not exceed one pitch in the
    perpandicular direction.
      To reduce an AutoSegment, call ::reduce() and to revert the state,
    call ::raise(). Two associated predicates are associated:
    ::canReduce() and ::mustRaise().
      Note: No two adjacent segments can be reduced at the same time.
* Bug: In Katabatic, in GCellTopology, add a new method ::doRp_AccessPad()
    to connect to the pads. Create wiring, fixed and non managed by
    Katabatic, to connect the pad connector layer to the lowest routing
    layers (depth 1 & 2). The former implementation was sometimes leading
    to gaps (sheared contact) that *must not* occurs during the building
    stage.
      Remark: This bug did put under the light the fact that the initial
    wiring must be created without gaps. Gaps are closed by making doglegs
    on contacts. But this mechanism could only work when the database if
    fully initialised (the cache is up to date). Otherwise various problems
    arise, in the canonization process for example.
* New: In Katabatic, in AutoContactTerminal::getNativeConstraintBox(),
    when anchored on a RoutingPad, now take account the potential rotation
    of the Path's transformation. Here again, for the chip's pads.
* New: In Kite, support for reduced AutoSegment. TrackSegment associateds
    to reduced AutoSegment are *not* inserted into track to become
    effectively invisibles. When a segment becomes reduced, a TrackEvent
    is generated to remove it. Conversely when it is raised a RoutingEvent
    is created/rescheduled to insert it. All this is mostly managed inside
    the Session::revalidate() method.
* New: In Kite, in KiteEngine::createGlobalGraph(), in case of a chip,
    mark all global routing vertexes (Knik) that are under a pad, as blockeds.
* Bug: In Cumulus, in PadsCorona.Side.getAxis(), inversion between X and
    Y coordinate of the chip size. Did not show until a non-square chip
    was routed (i.e. our MIPS R3000).
* Change: In Stratus1, in st_placement.py add the ClockBuffer class for
    backward compatibility with the MIPS32 bench. Have to review this
    functionnality coming from the deprecated placeAndroute.py.
      In st_instance.py, no longer creates the Plug ring of a Net.
    In my opinion it just clutter the display until the P&R is called.
    Can re-enable later as an option (in Unicorn).
* Change: In Unicorn, in cgt.py, more reliable way of loading then running
    user supplied scripts. Borrowed from alliance-checker-toolkit doChip.py	.
2015-08-16 23:29:28 +02:00
Jean-Paul Chaput ae6eeb8f56 Merged QuadTrees in overlayed Cells (placed together).
* New: In Hurricane, in Cell & Instance, add the ability to merge the
    QuadTree when *second level* instances of a Cell are placed in
    the same space as the top Cell. This is the case of a deeply
    hierarchical design made of only standard cells that are to
    be placed in a "flat" manner.
      The design is uniquified then the intermediate instances models,
    which should be unique at that point have their QuadTree merged
    through a call to Instance::slaveAbutmentBox(). That method will
    make the model of the instance use the QuadTree of the Cell to
    which the instance belong. The instance model no longer posseses
    a dedicated QuadTree. As a corollary the abutment box of both
    Cell are kept identical and the Instance has it's transformation
    set to (0,0,ID).
      Remark: when we talk about "QuadTree", we mean in fact the
    QuadTree for the instances *and* the SliceMap (Layer+QuadTree).
      Consequence in Query: when going through the resulting
    "flattened" QuadTree we will find objects with an incomplete
    Path du to the fact that we didn't have to explore their
    Instance/Cell level to reach them. The shunted part of the
    Path is stored in the Go master Cell in the _shuntedPath
    attribute. This also affect the displayed depth of hierarchy,
    but not too badly.
* New: In Hurricane, in Cell, new methods:
    - Cell::updatePlacedFlag() : set the placement flags.
    - Cell::isUnique() : one or less instance.
    - Cell::isUniquified() : is the result of an uniquification.
    - Cell::isUniquifyMaster() : is the reference cell of the
    uniquification.
* Change: In Hurricane, in Cell::Uniquify(), uniquify a Cell only
    if it is unplaced. We do not need to duplicate placed Cells
    (see datapathes).
2015-06-26 18:35:11 +02:00
Jean-Paul Chaput 6ecdaf2539 More accurate routing guiding under a block corona.
* New: In Kite, in BuildPowerRails more accurate GCell density computation
    under the pad area, to limit the overloaded messages.
* New: In Cumulus, In BlockCorona, remove the vertical METAL3 blockages
    and replace them by horizontal blockages completly enclosing the
    corona big vias in all layers. This way the I/O wires that goes
    through the corona are guided to be straight and do not creates
    unsolvable doglegs due to the presence of big vias.
* Change: In Kite & Etesian, small typo: refactor the method
    "::wipeOutRouting()" into "::wipeoutRouting()" (indulge me, I'm a
    code maniac).
2015-06-06 18:22:48 +02:00
Jean-Paul Chaput b1ca43fd57 Do not expand Clock Tree wires, may creates DRC violations. 2015-05-21 13:05:08 +02:00
Jean-Paul Chaput f8a72288aa Better handling of exceptions between C++ & Python. Misc. checks.
* Bug: In Hurricane, in PyHurricane.h the macro HCATCH was not catching
    standard STL exceptions. This was the source of the cryptic message:
        "Fatal Python error: Py_EndInterpreter: thread still has a frame"
    The Python interpreter was interrupted uncleanly bypassing it's own
    exceptions mechanism.
      In PyViewer, the Viewer *do not* inherit from a base class (in the
    Python export).
* New: In Hurricane, in DbU, compute maximum values (in double) for
    grid, lambda & physical (in meter) so now the DbU::toGrid(),
    DbU::toLambda() & DbU::toPhysical() methods can check for out of
    bound values, and throw an exception.
* Change: In Hurricane, ExceptionWidget::catchAllWrapper() now returns
    a boolean, set to <true> if an exception has been catched. Allow
    callers to interrupt themselves if a problem has occured.
* Bug: In Kite & Etesian, in the Python wrapper, send a Python exception
    if catchAllwrapper() did return true, instead of continuing...
* Change: In Kite & Etesian, adds a setViewer() method (exported in Python)
    to use the graphical ExceptionWidget when in graphic mode.
* Bug: In Cumulus, in PadsCorona.py the check for the core vs. chip size
    was not returning False when invalid.
* New: In CRL Core, in Vst driver, add a support IEEE VHDL. Inactive for
    now as I don't see clearly the policy for selecting it or not.
      Remove the code of the old Vst driver.
      In Blif parser, check for non-existent models (incomplete or
    corrupted Blif file). Found by G. Gouvine.
* New: Added extras file for IDE-like support under Emacs.
2015-05-20 14:03:59 +02:00
Jean-Paul Chaput 06e5e3060c Complete rewrite of the VHDL (Vst) driver. True handling of vectors.
* Bug: In Hurricane, in NetAlias, bad Record construction of the _next
    field.
* New: In CRL Core, in VstDriver complete replacement of the old Vst
    driver. Needed cleaner architecture to manage correctly files
    importeds through the Blif parser, which are Verilog like.
      It is build as an extension trough property and is not kept
    in sync with the Cell. So it's use should be transient only.
* Change: In CRL Core, in NamingScheme forgot to change '.' (dot)
    forbidden character into '_'.
* Change: In Cumulus, in the RSave plugins, remove the VHDL extensions
    after saving.
2015-05-02 18:39:35 +02:00
Jean-Paul Chaput 4023481da3 Add a state to Cell to know if is placed and/or routed.
* New: In Hurricane, In Cell, add Placed and Routed flags to know the
    state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
    external connectors if the design is *not* routed (create
    conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
    has a bounding box.
2015-04-16 16:52:33 +02:00
Jean-Paul Chaput ef9936e87c Support for Net alias names. Blif parser enhancements.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
    Use a structure based on a simple ring of NetAliasHook. The Net
    holds a global map, sorted by names of all the aliases of all Nets.
    Elements NetAliasesHook of the map are slaves of ring whose master
    is an attribute of the Net (it is *not* in the map, as the primary
    name of the Net).
      In case of merge, the aliases of both Nets are merged and the
    name of the merged one become an alias.
      The Cell::getNet() looks in both the Net map and the aliases to
    find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
    configuration files so the real technology is read as early as
    possible to set up the <gridsPerLambda> factor before any lambda
    is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
    has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
    a design into VHDL compliant names (mainly from Blif/Verilog).
    This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
    messages. Align the loading progress information on the other
    parsers.
      Add a capability to select which component of the design will
    be returned, if there are more than one. Use the "." as separator.
    For exemple you can request "Processor.Alu", which will load
    the "Alu" component from the design in "Processor.blif".
      To be able to save a Blif loaded design, systematically convert
    all the name for VHDL compliance, as it is the format used by
    the Coriolis native files (vst).
      Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
    remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
    the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
    Partly redundant with the previous one. Have to better organize
    that later.
2015-04-16 15:40:02 +02:00
Jean-Paul Chaput 393b5a735f Remove simulated annealing placer Nimbus/Metis/Mauka. 2015-03-17 22:50:00 +01:00
Jean-Paul Chaput 5dc60415e7 Happy new year 2015! 2015-03-17 16:56:55 +01:00
Jean-Paul Chaput f5020120bf Correct clock-tree building when used on a standalone block.
* Change: In Cumulus, in Configuration.py, in the horizontal & vertical
    wire creation adds new flags ExpandWidth to draw wires one lambda
    bigger than the minimal width (see ClockTree.py patch).
* Change: In Cumulus, In ClockTree.py, use non default width to draw
    wires of the H branch of the clock tree. This is to prevent them
    to be recognized as "manual global routing", which they are not
    and not event topologically compatible.
* Bug: In Kite, in BuildPowerRails, change the way clocks are detected
    when working on a single block (not a whole chip). Now look only
    in clock which are external and do not filter out already routed
    ones.
* Change: In KiteEngine, in createGlobalGraph(), systematically call
    flattenNets() so nets that are added after the first flattening
    in the placer are also flattened. The flattenNets() Cell method
    takes care of not flattening twice a net.
2015-03-03 11:11:22 +01:00
Jean-Paul Chaput 8566126acc Adding Configuration support to Etesian.
* Change: In Bootstrap & ccb, the coloquinte project is renamed into
    "importeds", it will be the home of all the externally
    devellopped softwares that are needed to build Coriolis.
      Add explicit support for Fedora ("Linux.fc") and uses
    site-packages, as everybody else.
* New: In CRL Core, in etc/, adds the configuration files for Etesian.
* New: In Etesian, activate the Configuration object. Now uses it's
    own configuration variables instead of borrowing those of
    Nimbus & Mauka.
* Change: In Documentation, updated User's Guide to present Etesian
    as the placer, instead of Mauka.
* Change: In Cumulus, slight change in ClokTreePlugin and ChipPlugin
    to match the new Etesian/Python interface.
2015-02-27 18:16:03 +01:00
Jean-Paul Chaput 6d366a08bc Etesian integration with Chip & ClockTree plugins.
* New: In Hurricane, in DebugSession, add a new method to activate the
    trace inconditionally with a certain level.
* New: In Hurricane, in HyperNet, allow copy construction as there is
    no reason to disallow it and we need it now.
* New: In Hurricane, in Cell::flattenNets(), add a new option to prevent
    the flattening of the clock net(s). For more safety perform the
    DeepNet creation *outside* the Collection loop.
* Bug: In Hurricane, in Cell_HyperNetRootNetOccurrences, skip the
    DeepNets because they are the result of another flattening operation.
* New: In Isobar, in PyBasicLayer, export C++ method getBlockageLayer().
* New: In Isobar, in PyRoutingGauge, export C++ method getLayerPitch(),
    needed by Cumulus plugins.
* New: In Etesian, EtesianEngine::findYSpin() to look for the Y orientation
    if some cells are already placed. Typically the buffers of a clock
    tree.
      Pass the correct orienation to row_compatible_orientation().
      Do not try to add feeds in the ISPD05 benchmarks. For now the
    benchmarks are detected through their names (unreliable).
* Change: In Knik, in KnikEngine::initGlobalRouting(), allow the clock
    to be routed as an ordinary signal when the clock tree is not
    used.
* New: In Kite, in BuildPowerRails, management & detection for the
    pre-routed clock.
      In KiteEngine constructor, early initialization of the blockage
    net to avoid later troubles in BuildPowerRails.
* New: In Cumulus, in ChipPlugin, add support for Etesian plus new
    configuration parameter 'clockTree.placerEngine' to select between
    Mauka and Etesian.
* New: In Cumulus, in BlockCorona, add blockages in the vertical sides
    in the vertical layer to prevent the router to use the vertical
    tracks in under the prower lines (for example, blockage in M3
    with power line M5).
      In Cumulus, in ChipConf add attribute to access the blockage net.
* New: In Cumulus, when the clock tree is disabled, do not generate
    the last rail around the block (the clock rail).
* Bug: In Cumulus, in ChipConf use the clock pad to guess the clock
    signals and *not* the power pad.
      Add more meaningful error messages if a pad global signal is
    not found (implicit connexion by name).
* Bug: In Cumulus, in ClockTree, compute correctly the cells Y spin,
    that is *from the bottom of the cell AB* (not from 'zero').
2015-02-24 13:13:17 +01:00
Jean-Paul Chaput 3b343f08cf Bug in Python proxy deallocation. Update to latest Coloquinte.
* Bug: In Bootstrap, in coriolisEnv.py, check if devtoolset-2 is already
    active before launching it as a sub-shell.
* Bug: In Isobar, In PyHurricane.h, DBoDestroyAttribute() set the proxy
    pointer toward the C++ object to NULL. So when the Python object is
    deleted no double-deletion occurs on the C++ object.
      Add some more trace information in Python link/dealloc.
* Change: In CRL Core, in cyclop, make CMakeLists.txt automatically
    choose the right rule for linking the binary wether we use Qt 4 or
    Qt 5. Very irksome problem.
* New: In EtesianEngine::addFeed(), do not take into account instances
    that are not placed entirely inside the top cell abutment box (was
    causing a core dump).
* Bug: In Katabatic, in GCellQueue, correct a mismatch between a GCell
    set and the iterators used upon it.
* Bug: In Mauka, in Row & Surface correct a mismatch between a container
    and it's iterator.
* New: In Etesian, updated to work with the latest Coloquinte, patch
    contributed by G. Gouvine.
      Added EtesianEngine::setDefaultAb() to compute an abutment box if
    the Cell is completly unplaced.
* New: In cumulus, in ClockTree, now the placer can be configured to be
    either Mauka (slow simulated annealing) or Etesian (fast analytic).
    New setting 'clockTree.placerEngine' in plugin settings.
2015-02-13 23:38:55 +01:00
Jean-Paul Chaput b18219d807 Integration of the latest Coloquinte in Etesian & misc modifs.
* New: In Bootstrap, in Builder & coriolisEnv.py support for RHEL7/SL7.
    The sub-directory name is 'el7_64'.
      In qt_setup() add QtSvg to list of Qt5 & Qt4 used libraries.
* New: In Hurricane, In Cell add a placeholder for flags. First use to
    store whether the Nets have been transhierarchically flatteneds.
* New: In Hurricane, In NetRoutingState add an Unconnected flag for
    more accurate diagnosis.
* New: Hurricane, in CellViewer add an entry menu for stress tests.
    The script must be named "stressScript.py" in the cwd.
* Change: In CRL Core, in display.conf add a scaling parameter for the
    display threhold of the layer. This way we can adapt to different
    standard cells height.
* Change: In CRL Core, in ISPD05 bookshelf loader, use the pitch of the
    cell gauge instead of a hard-wired 5.0.
* Change: In Cumulus, in ClockTreePlugin, add support for Etesian placer
    and a new configuration parameter to choose between Mauka/Etesian.
* New: In Etesian, support for the latest Coloquinte.
    Add feed insertion stage.
* Bug: In Kite, In BuildPowerRails, check that _ck is not NULL before
    tring to access it's name...
* Change: In Kite, check if the Cell has it's Nets flattened before
    doing it (or not).
2015-02-01 23:24:13 +01:00
Jean-Paul Chaput 56bd484429 In BlockPower, manage correctly a block without clock tree. 2014-12-12 18:40:53 +01:00
Jean-Paul Chaput 648b85226e Use rowend instead of tie in ClockTree for removed clock buffers.
* Bug: In Cumulus, in ClockTree.py, do not use "tie_x0" which is 2 pitch
    wide to fill the free space left by clock-tree removed (unused)
    buffers. If the buffer size width is odd (in pitch), it will left
    a gap in the WELL. That was the cause of DRC notch errors.
      Instead use "rowend_x0" which is one pitch wide.
      Should use the same mechanism as in Mauka InsertFeed.
2014-10-02 00:42:59 +02:00
Jean-Paul Chaput 1f9ae36554 Bug fixes for MOSIS SCMOS_DEEP support.
* Change: In Hurricane, the NetRoutingProperty is moved into Hurricane
    from Katabatic. Needed for Knik to be able to access thoses
    informations.
* Change: In Hurricane, in RoutingPad::setOnBestComponent(), now in
    case of identical area, select the component of lowest id.
    This should not be needed if the component ordering was fully
    deterministic as it should be (will investigate later).
      This is to ensure that the choosen component is always the
    same, especially between save/load of a global routing.
* Bug: In Katabatic, in AutoContactHTee::updateTopology(), invalidate
    the segments only if the topology is valid (no NULL in the
    cached segments).
* Bug: In Katabatic, in GCellTopology::construct(), throw an error
    if the topology is bad instead of trying to continue (and core
    dump later... ).
* Bug: In Kite, in BuildPowerRails, distinguish the name of the master
    net in the pad (for vddi, vssi, vdde, vsse, ck, cki & cko) and the
    name of the net in the *chip* netlist. Must use the later to make
    comparison as they may differs.
* Change: In Knik, in save/load solution, exclude nets that are not
    globally routed by Knik. That is which NetRoutingProperty is not
    *Automatic*.
* Bug: In Cumulus, in chip.BlockPower take account of the layer
    width extention to sligthy shrink the connector thus avoiding a
    notch with standart cell in some cases.
* Change: In Cumulus, in chip.ClockTree disable the use of fixed Steiner
    trees for the leaf clocks, as it seems overconstrained for the
    router. First move was to lower them in M2/M3 (instead of M3/M4)
    but that was not sufficent.
* New: In Cumulus, RSavePlugin for recursively saving a physical
    hierarchy.
* New: In documentation, first embryo for RDS file. Should have been
    in Alliance git, but I prefer to keep newest doc in Coriolis.
2014-09-21 16:44:37 +02:00
Jean-Paul Chaput 2c345c9033 Various improvement & bug correction in Katabatic & Kite.
* Bug: In Katabatic, in AutoContactTurn::cacheAttach() unset the
    "cache invalidated" flag *only* if the h1 & v1 component are
    sets. This is needed because we can attach *before* the first
    cache revalidation (in the initial building stage).
* Bug: In Katabatic, in AutoSegment::getPPitch() out of bound access
    of the top of the RoutingGauge, in case of a top layer segment
    with a spin top flag (maybe this shouldn't happen?).
* Change: In Kite, in SegmentFsm::conflictSolveByPlaceds() take
    account as conflicting other global, global, blockage *and*
    now fixeds.
* Change: In Cumulus, in px2mpx.py more accurate way of transforming
    the pad blockages.
2014-09-14 18:54:10 +02:00
Jean-Paul Chaput a3963716b1 Correction in plugins to support msxlib compatible pads.
* New: In CRL Core, in helpers & alliance.conf, set and read a "PAD"
    variable to define the pad model name extension ("px" for "sxlib
    and "pxr" for vsxlib, this is provisional).
* New: In CRL Core, in plugin.conf, add parameters to define the name
    of used for power & clock supply. We may remove the extention in
    the future (to be more coherent with the previous modification).
* New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no
    longer place the accessing contact *at the center* of the
    RoutingPad. It works under sxlib because buffers & registers all
    have same size terminals. But this is not true under vsxlib,
    leading to misaligned contacts & wires. Now systematically place
    on the slice midlle track (maybe with one pitch above or below).
      This is still very weak as we do not check if the terminal
    reach were the contact is being put. Has to be strenthened in
    the future.
* New: In Cumulus, in chip.Configuration.ChipConf, read the new
    clock & power pad parameters.
* Change: In Isobar (and all other Python wrappers), uses PyLong instead
    of PyInt for DbU conversions. In PyHurricane argument converter,
    automatically check for both PyLong and then PyInt.
* Change: In Cumulus, in chip.PadsCorona, more accurate error message
    in case of discrepency in global net connections (i.e. no net
    of the same name in instance model and instance model owner.
* Change: In Kite, in BuildPowerRails, when looking up at the pads
    model name to find "pck_" or "pvddeck_", do not compare the
    extension part. But we still use hard-coded stem pad names,
    maybe we shouldn't.
* Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there
    was a loop in the search of the best N/E initial RoutingPad.
* Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect
    RoutingPads of fixed nets, they are already through the
    BuildPowerRails stage (and it's causing scary overlap warning
    messages).
* Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create
    deep-plug when the core is flat (not sub-modules). All the new
    nets are at core level.
* Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure
    that the core is aligned on the GCell grid (i.e. the slice
    grid of the overall chip).
* Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop
    while looking for the bigger N-E RoutingPad. Forgot to decrement
    the index...
2014-09-13 17:45:30 +02:00
Jean-Paul Chaput f85159bdb4 More accurate error message in Python module importation. 2014-09-07 23:16:04 +02:00
Jean-Paul Chaput c26a36db88 In ChipPlugin, do not call the editor if it's not there. 2014-09-04 10:59:09 +02:00
Jean-Paul Chaput e6c809a12a Correct loading of clock buffer in ClockTree plugin.
* Bug: In ClockTree plugin, only the logical view of the clock buffer
    was loaded, so no external components where found on the I/O nets.
    The external components are loaded only when the *physical* view
    is loaded. Didn't show on sxlib because the buffer was fulled
    loaded *before* running the ClockTree.
* Bug: In PyHurricane, in the various LocatorNextMethod() macros,
    sometimes an empty collection can be returned by Hurricane
    (GenericCollection()), which has a NULL locator. So check
    if the locator is *not* NULL before trying to access it...
* Change: In Chip, more accurate error messages related to the clock
    detecttion.
2014-09-03 10:37:11 +02:00
Jean-Paul Chaput ae4d938553 Buffer cell configuration in ClockTree. More config parameters in Chip.
* New: In ClockTree plugin, select the name of the buffer cell through
    configuration (parameter: "clockTree.buffer"), and guess the I/O
    name of this buffer automatically.
      Put configuration parameters in plugin.conf and not mauka.conf.
      Bug: strangely triggers a coredump in components collection
    when used with <vsxlib>. Some debug printing still active until
    that is solved.
* New: In Chip plugin, make the size and numbers of the block rails
    configuration parameters (in plugin.conf).
2014-09-02 11:17:47 +02:00
Jean-Paul Chaput 51a3236962 Add management of fixed wires to Kite (for chip ClockTree)
* Change: In Hurricane, in Plug::setNet(), more informative error messages.
* Change: In Hurricane, In Segment, more informative error messages.
* Change: In Hurricane, In DeepNet, accessor for the Net occurrence.
* Bug: In Katabatic, in AutoSegment::create(), error message uses correct
    variables (vertical was using horizontal)...
* Change: In Kite, in BuildPowerRails, already existing wiring in instances
    is copied up as blockage. Uses blockage layer instead of true layer
    (it was a bug).
* Change: In Kite, in BuildPreRouted, consider as manual global routing
    nets with only default wiring (default size wire & contacts).
    Non-default routing is flagged as fixed (with the NetRoutingState
    property).
2014-08-15 19:26:49 +02:00
Jean-Paul Chaput fb4a7457a1 First basic version of ClockTree & Chip plugins.
* New: In Cumulus, first versions of the ClockTree and Chip plugins.
    Clock Tree plugin:
    - It is strongly advised to use have 4 metal routing layers for the
      tree to work. Otherwise, problems can arise with the detailed
      routing (fully obstructed terminals).
    - H-Tree can only be build (for now) for design with a form factor
      between 0.5 an 2.
    - The tree is created at the block top-level and only the leafs are
      trans-hierarchically created on the instances/models. The new
      cell with a clock tree, along with all it's sub-models is created
      with a "_clocked" suffix.
    - Leaf cells are connected through a simple Minimum Steiner Tree.
    - Shorts are avoided by a systematic shift of the wires according
      to their kind. No wire must pre-exist. When used as a sub-module
      of "chip" the wires cannot be moved. When created on a block,
      the wires can be loaded in the detailed router as manual global
      router.
    Chip Plugin:
    - Perform the pad placement and corona creation. Replacement at
      last of the clunky code from Wu Yifei.
    - Relies on a Python configuration file '<design>_chip.py' with
      a "chip" dictionnary.
2014-08-15 19:05:27 +02:00
Jean-Paul Chaput 0fab6087fa Start of Alliance/Python encapsulation layer.
* New: In Cumulus, new Alliance.py module (*not* a plugin) providing
    an encapsulation for Alliance command line tools. The other main
    feature is that it provides a "Makefile like" behavior. Based on
    the command dependencies a DAG is contructed, then a static
    ordering of the commands. Commands are then executed to rebuild
    outdated target.
      The Alliance environment supplied to the commands is read from
    the Coriolis configuration file <alliance.conf>.
      For this first evaluation version, only <boom>, <boog> and
    <loon> support are provided.
      It still not clear how to encapsulate the Coriolis tools in
    the same way.
* Change: In CRL Core, in helpers/__init__.py, change the way the static
    initialization (module) is done. All the commands are put inside
    a "staticInitialization()" function, which is then explicitly
    called by others. This is a better solution agains *no* or *twice*
    initialization. Modificate <coriolisInit.py> accordingly (as
    <Alliance.py> from Cumulus.
2014-07-27 16:23:27 +02:00
Jean-Paul Chaput 25e82fc701 Complete replacement of the Chip placement Python scripts.
Finally get rid of the demonic code from Wu Yifei...
* New: In Isobar, added encapsulation of Interval (don't know how have
    forgotten it for so long).
* Change: In Isobar, In PyLayer, new PyLink_LayerDerived() function to
    create/link the C++ object to the correct derived class and not the
    base one (PyLayer) which then prevent to use the specialized methods.
    Must replace PyLink_Layer() througout all the code.
* Change: In Isobar, in PyPoint the "setX()" & "setY()" methods where
    still capitalized.
* Change: In Isobar, in PyQuery, complete the exportation of the C++
    interface. remove the code belonging to a more "boost" way of
    building the Python interface (will do that in a far future).
* New: In CRL Core, In PyAllianceFramework, export isPad() method.
* Change: In Unicorn, in unicornInit.py, protect the loading of each
    single plugin by a "try" / "except" clause to the failing of one
    plugins do not stop the loading of the next one.
      Pass the same dictionnary argument to unicornHook() as for
    ScripMain(), this is more uniform this way.
* New: In Cumulus, complete replacement of the chip placement scripts
    from Wu Yifei (at last!). The clock-tree integration is still to
    be done.
________________________________________________________________________
2014-07-21 13:18:34 +02:00
Jean-Paul Chaput d0d045b55b Starting to implement support for Windows/Cygwin.
* New: In all to CMakeLists.txt, disable the warning about deprecated
   WIN32 under cygwin.
* New: In boostrap, in ccb.py, coriolisEnv.py and builder/Configuration.py
   add recognition in uname for the values returned under Windows/Cygwin.
* New: In Documenation, in UsersGuide.rst add some informations about
   Cygwin and a section for the devel branch.
2014-07-13 13:14:49 +02:00
Jean-Paul Chaput 7296dcd6fb Make the Python interface closely mirroring the C++ one.
* Change: In Isobar, the Python interface was not exactly mirroring the
    C++ one, now it is the case. The Python code should look likes almost
    exactly like the C++ one, the only differences remaining being due
    to the languages respective syntaxes. Note that in the case of
    constructor functions, it leads to a slightly longer notation in
    Python that it could have been (mimic the ".create()" static
    member). Main modifications:
    1. Mirror the static constructor syntax with create():
          Cell( ... )   ==>  Cell.create( ... )
    2. Correct hierarchy for constants in Instance, Net, Pin
       & Transformation. For example:
          Hurricane.PlacementStatusFIXED
                     ==> Hurricane.Instance.PlacementStatus.FIXED
          Hurricane.OrientationID
                     ==> Hurricane.Transformation.Orientation.ID
          Hurricane.TypeLOGICAL  ==>  Hurricane.Net.Type.LOGICAL
          Hurricane.DirectionIN  ==>  Hurricane.Net.Direction.IN
* Change: In CRL Core, correction to match the improved Python API
    in the configutation helpers.
* Change: In Cumulus, correction to match the improved Python API.
* Change: In Stratus, correction to match the improved Python API.
* Change: In Documenation, update for the new Python interface
    (both user's guide & examples).
* Note: We must port those changes into Chams for it to continue
   to run.
* Change: In Documenation, update the Python script support part.
2014-06-29 14:26:59 +02:00
Jean-Paul Chaput 01b97626a8 Support for Python plugins in CellViewer/Unicorn. ClockTree plugin.
* New: In Hurricane, in CellViewer, create a simpler API to graft menu
    and actions into the menubar. Mainly addToMenu() which take care of
    the QAction creation but also locate the relevant QMenu, base on
    the Qt object name. Regroup all the widget & action creation inside
    the body of the constructor, this way almost all actions can be
    removed from the attributes of the CellViewer.
      addToMenu() is supplied in three flavors:
        1. For C++ callbacks in GraphicToolEngines (with a binded
           member function method).
        2. For running Python scripts to be used by the plugin system.
        3. To insert separator in menus (to give a more homogeneous
           look).
    Remove the last remnants of Stratus scripts (unificated with basic
    Python scripts).
* New: In Hurricane, in PyCellViewer, export the interface to graft
    Python scripts into the CellViewer menu tree.
* Change: In Etesian, in GraphicEtesianEngine, use the new API to
    graft menus & callbacks into the CellViewer.
* Change: In Mauka, in GraphicMaukaEngine, use the new API to
    graft menus & callbacks into the CellViewer.
* Change: In Kite, in GraphicKiteEngine, use the new API to
    graft menus & callbacks into the CellViewer.
* New: In Cumulus, install Python scripts as plugins for Unicorn under
    <PYTHON_SITE_PACKAGES>/cumulus/plugins/.
* New: In Unicorn, in UnicornGui, make uses of the new API for creating
    menus in the CellViewer. Creates the stem menu for the P&R tools.
      Add a Python initialization mechanism to read the plugins
    installeds into <PYTHON_SITE_PACKAGES>/cumulus/plugins/.
2014-06-25 19:50:34 +02:00
Jean-Paul Chaput c8bcfdf174 Improved UpdateSession & exception catching. Start of RoutingGauge implem.
Miscellaneous:
* Change: In <crlcore>, in display.conf use the same display threshold
    for both METAL2 & METAL3.
      In alliance.conf, the side of VIAs in the gauge is 2l (not 3l).
      In kite.conf, separate edge densities for H/V.
* Change: In <Cell>, in flattenNets() use flag as argument, not a
    boolean. Do not create rings for clock or supply nets.
* Change: In <DeepNet>, in _createRoutingPads() do not create rings
    for clock or supply net (duplicated policy as in Cell::flattenNets()).
* Bug: In <ControllerWidget>, at last find the bad signal disconnect
    that was causing ungraceful messages.
* Change: In <knik>, in Edge display occupancy/capacity in the string
    name. Improved display progress and debugging capabilities.

Improved exception catch & breakpoint managment:
* Bug: In <PaletteWidget>, in updateExtensions() replace the calls to
    deleteLayer() by delete. This cause the widget to be immediatly
    erased instead of waiting for the event queue to be completly
    processed. This was causing the widget to be left in a incoherent
    state when stoping at a breakpoint.
* Bug: In <BreakpointWidget>, in execNoModal(), flush the main event
    loop (QApplication::flush()) *before* lauching the *local* event
    loop. This is to ensure all widgets are in their final state when
    waiting (especially <PaletteWidget>).
* Change: In <ExceptionWidget>, new method catchAllWrapper() to
    execute any std::function< void() > function/method with a "try"/
    "catch" wraparound and lauch the widget in case something is catch.
* New: In <hurricane>, support for a oberver pattern, backported from
    <katabatic> with an Obervable capable of being linked to any
    number of Obervers.
* New: In <Cell>, made it observable to detect Cell change, currently
    emit two kind of signals:
    - Cell::CellAboutToChange : *before* any change.
    - Cell::CellChanged : *after* the change has been completed.
* New: In <UpdateSession>, in Go::invalidate() add the Cell owning the
    Go to the UPDATOR_STACK (of course the cell is added only once).
    In addition, when the Cell is added, send a notification of
    Cell::CellAboutToChange to all it's observers. The slave instances
    are also invalidated.
      Conversely in UpdateSession::_preDestroy() for each invalidated
    Cell send a Cell::CellChanged notification to all observer.
      The UPDATOR_STACK has been slightly amended to accept Cell which
    are not Gos. Prior to this, the Cell where completly excluded from
    the UpdateSession mechanism, so it's instances where never actualised
    of anything referring to the Cell for that matter.
      Note: we use two different mechanisms to transmit a Cell change,
    observers and the slave instance map. I think at some point it
    should be unificated.
* Change: In <CellViewer>, make it a Cell observer to redraw when the
    cell is modificated (also update the palette).
      Uses the catchAllWrapper() to protect all critical actions.
* Change: In <GraphicTool>, no longer need of cellPreModificated and
    cellPostModificated signals. Now done through the Cell obersvers.
* Change: In <mauka>, <etesian> & <kite> now uses the catchAllWrapper
    method for protection (need to split methods in two, to be able
    to pass it as argument). No longer emit cellPreModificated and
    cellPostModificated.

Support for RoutingGauge in P&R:
* Bug: In <placeandroute.py>, the connection from the internal power
    ring to the connectors was not done correctly. Wrong contact layers
    leading to a gap.
* Change: In <BuildPowerRails>, detection of the corona signals based
    on how the "pck_px" pad is connected. No longer based on name
    matching.
* Change: In <placeandroute.py>, support for 2 routing metal only
    (3 metal in the technology).
* Change: In <katabatic> & <kite> support for a "top layer" limitation
    on the routing gauge, this allows to use only two routing metals
    (METAL2 & METAL3). Work in progress.
2014-04-20 19:30:07 +02:00
Jean-Paul Chaput f6ab7b87f0 Compliance with g++ 4.8.1, support for devtoolset-2
Details:
* New: in <bootstrap>: add support for devtoolset-2 in ccb. Run the
    cmake commands through 'scl', set shell environment variables
    BOOST_INCLUDEDIR & BOOST_LIBRARYDIR and disable the default
    system path search.
* Change: In various flex scanners add the %nounput to suppress
    compiler warnings.
* Change: Little cleanup for g++ 4.8.1 as it's more strict.
* Change: In various top CMakeLists.txt, suppress extraneous '/'
    after DESTDIR.
2014-03-15 10:47:37 +01:00
Jean-Paul Chaput 34e0edfd61 Cleanup after SVN importation, <ccb> builder script adaptation.
Project hierarchy reorganisation:
* With svn, we were doing a tool by tool checkout, suppressing the
  whole repository hierarchy level.
* The tools were also grouped, inside one repository, into multiple
  projects (<bootstrap>, <vlsisapd>, <coriolis>).
* We do not want to split up each tool into a separate repository,
  given their tight integration (except for vlsisapd).
* We choose to simplify, and consider all tools in a svn repository
  one project. Due to the way Git clone repositories, the directory
  containing the project is now to be seen under "src/".

CMake modifications:
* Now that the <vlsisapd> and <bootstrap> projects are merged into
  coriolis, modificate the top CMakeLists.txt of each tool to uses
  only Coriolis (and bootstrap hard wired).

CCB compile script modifications:
* Uses the new source tree hierarchy, with the project directory
  inserted.
* Remove (comment) all parts relateds to svn managment.
* Git is sufficiently simple so that we do not want to integrate
  command shortcut into the script.

SVN cleanup:
* Remove the obsolete <chamsin> tool, that has become the full fledged
  <chams> project long time ago.
2014-02-26 18:24:41 +01:00
Jean-Paul Chaput 21e0548fe9 * ./cumulus:
- Change: In placeandroute.py, uses variables for the clock grid VIAs sides...
2012-12-14 15:36:35 +00:00
Jean-Paul Chaput 94a52bd09c Reduce VIA size of the clock routing grid in M4/M5 to not
interfere with standard routing.
2012-12-11 10:27:13 +00:00
Jean-Paul Chaput c72726a0c2 * All Tools:
- New: Added FreeBSD/Ubuntu patches from Otacilio De Araujo
       (<otaciliodearaujo@gmail.com>).

  * ./cumulus:
    - Change: In placeandroute.py, raise ErrorMessages (from crlcore) instead
        of deprecated strings.
    - Change: In pyRouteCk, the clock grid now systematically covers the core
        area instead of only the area where clock signals are useds. This is
        to alleviate the constraint of alignement on the pvsseck pads (they
        must be in direct regard of the clock grid).
2012-12-03 08:30:49 +00:00
Jean-Paul Chaput b09ad0c40a * All Tools:
- A complete sweep of cleanup to suppress allmost all compiler warnings.

  * ./cumulus/placeandroute.py:
    - Change: Uses the new "create()" method.
2012-11-16 12:50:44 +00:00
Jean-Paul Chaput 81f3b2fa56 * ./cumulus:
- Bug: In placeandroute.py/createGrid(), VIAs of the big clock grid must
        have the same width as the wires (12l). But due to the layer extension
        the VIA side must be of 11l.
    - Bug: In placeandroute.py/createGrid(), wires connecting cell clock pin
        to the clock trunk must respect the preferred routing direction.
        The only exception being when the wire is completly enclosed under
        the trunk wire. This is for the obstacle stage of the detailed router.
2012-01-02 21:20:36 +00:00
Jean-Paul Chaput aa92e0b4f7 * <All Tools>/CMakeLists.txt:
- Change: For the setup_sysconfdir() boostrap/cmake macro uses the
        CMAKE_INSTALL_PREFIX to guess where we are being installed.
        Should be more reliable than any *_TOP environment variable.
2011-02-15 13:16:15 +00:00
Jean-Paul Chaput 7108bc716b * <All Tools>/CMakeLists.txt:
- Bug: During the packaging stage, DESTDIR must be appended to the
        pathes prepended to CMAKE_MODULE_PATH.
2011-02-02 11:44:17 +00:00
Jean-Paul Chaput 5b7b078688 * ./cumulus:
- Bug: Uses correct Contact with for rings.
    - Bug: Reorder import so that CRL is always imported first so that the
        problem of duplicated type_info RTTI doesn't show.
2010-11-16 14:09:31 +00:00
Sophie Belloeil 3980024386 No more setup_apple() 2010-07-22 14:37:26 +00:00
Jean-Paul Chaput 80c0a0fa5e Re-enable temporarySave() to save intermediate layouts.
Ugly.
2010-07-20 12:19:27 +00:00
Jean-Paul Chaput 72e63309e7 * All Main Python Modules:
- Change: New problem identified with the Python modules: each module seems
        to be built as a complete binary, so all the static C++ initializers are
        allocated in each module. In particular the C++ tree inheritance is built
        for *each* module so we cannot longer uses the typeid() comparisons
        across modules... It was used by boost::program_options to perform is
        casts with boost::any and was starting throwing exceptions because of
        bad casts. program_option was first initialized in "configuration"
        first included by PyViewer then in PyCRL (see Utilities.cpp).
          A first solution is to re-order the import of Python modules in
        stratus1/st_model so that CRL is imported first.
          The second is to not not link "configuration" with boost::program_option
        as only the binary vlsisapd-conf-editor needs it.
          That is a serious problem of which we must be aware and can cause further
        strange behaviors.
          Debug code used to diagnostic has been kept commented in the sources a
        it may be needed again :-(
          This behavior do not affect our singletons because they are part of
        dynamic libraries that seems to be correctly shared between the various
        Python modules.

  * ./stratus1,
    ./cumulus:
    - Change: Replace calls to CRL.getAllianceFramework() by CRL.AllianceFramework.get().
2010-07-17 10:34:46 +00:00
Jean-Paul Chaput f05957c03c * All Tools:
- Change: Using more Bootstrap macros. Simpler way of setting the
        CMAKE_MODULE_PATH.
2010-07-15 14:40:23 +00:00
Jean-Paul Chaput c6f2e533b8 Forgoten minimal cmake version required. 2010-07-15 12:33:18 +00:00
Jean-Paul Chaput 05accbabbe * All Tools:
- Change: Switch from "goodies" to "bootstrap".
2010-07-14 19:48:12 +00:00
Jean-Paul Chaput 9ecac8f9f6 All tools: using the new Goodies macro.
Suppress loops in Hurricane libraries.
2010-07-13 16:34:16 +00:00
Jean-Paul Chaput c1ab67d1ac Initial import of cumulus 2010-07-12 15:31:29 +00:00