Commit Graph

2695 Commits

Author SHA1 Message Date
Robert Taylor d8e67e5e7d Reduce debug output 2023-02-21 16:10:55 +01:00
Robert Taylor f0cd6e602a Use ninja for build 2023-02-21 16:10:55 +01:00
Robert Taylor d10b7524ce remove cylop and cx2y from scripts 2023-02-21 16:10:55 +01:00
Robert Taylor fa1f8e78e0 CI: only build cpython >= 3.8 2023-02-21 16:10:55 +01:00
Robert Taylor 32a6aaf61f Ignore missing symbols harder when linking python 2023-02-21 16:10:55 +01:00
Robert Taylor 7a8a3d3434 Always pass build type 2023-02-21 16:10:55 +01:00
Robert Taylor 8f8671c8fb Only build cycop and x2y when in debug build 2023-02-21 16:10:55 +01:00
Robert Taylor a02c88a893 Don't link libpython, it isn't there in manylinux 2023-02-21 16:10:55 +01:00
Robert Taylor eb26bb1f87 fix to build on manylinux 2023-02-21 16:10:55 +01:00
Robert Taylor 6088ab7b69 Split out python versions in CI 2023-02-21 16:10:55 +01:00
Robert Taylor c22dfe3216 Pass in python library path to cmake 2023-02-21 16:10:55 +01:00
Robert Taylor 095e260e3b Use target_link_libraries correctly everywhere to avoid runtime link issues 2023-02-21 16:10:55 +01:00
Robert Taylor 974473aff7 fix rpaths - really didn't need quoting 2023-02-21 16:10:55 +01:00
Robert Taylor 78f4107f36 Update poetry lock 2023-02-21 16:10:55 +01:00
Robert Taylor 0868283e43 Fix runtime linking error 2023-02-21 16:10:55 +01:00
Robert Taylor 4e879b4506 RPATH for libraries to find other coriolis libs 2023-02-21 16:10:55 +01:00
Robert Taylor 412f9bb22d Fixes for cibuildwheel building 2023-02-21 16:10:55 +01:00
Robert Taylor e1736fcdba Support older qwt 2023-02-21 16:10:55 +01:00
Robert Taylor 7789c6db80 update poetry lock 2023-02-21 16:10:55 +01:00
Robert Taylor 52f64bc9d3 Use the running python for cmake 2023-02-21 16:10:55 +01:00
Robert Taylor 2b88f8188c try dropping python dependancy and see what breaks 2023-02-21 16:10:55 +01:00
Robert Taylor e7fcfd1a44 Add gitlab CI using cibuildwheel 2023-02-21 16:10:55 +01:00
Robert Taylor 29add5e898 Fix tutorial for python 3 2023-02-21 16:10:55 +01:00
Robert Taylor 05c0f955c5 Fix up rpath of binaries 2023-02-21 16:10:55 +01:00
Robert Taylor c6795754a1 Move into Corilois namespace 2023-02-21 16:10:55 +01:00
Robert Taylor a3abb567b5 Add version and author to pyproject.toml 2023-02-21 16:10:55 +01:00
Robert Taylor 424c61d6a4 Fix errors when building clean 2023-02-21 16:10:55 +01:00
Robert Taylor ebabf1e988 install helpers at top level 2023-02-21 16:10:55 +01:00
Robert Taylor df78c3ab48 Add bin files as scripts 2023-02-21 16:10:55 +01:00
Robert Taylor 5a669c4641 Fix Python linking issues 2023-02-21 16:10:55 +01:00
Robert Taylor b07bf75283 Give same import semantics for now, fix rpath issue 2023-02-21 16:10:55 +01:00
Robert Taylor ee2e18f801 Add Coriolis dir that poetry needs, along with base __init__.py 2023-02-21 16:10:55 +01:00
Robert Taylor d614e490e7 Poetry package build working for most of coriolis 2023-02-21 16:10:55 +01:00
Robert Taylor f8afd5bded Move to packaging requiring no changes to CMake 2023-02-21 16:10:54 +01:00
Robert Taylor 806018b740 Initial Poetry infrastructure 2023-02-21 16:10:54 +01:00
Robert Taylor 858a783ddd Move decprecated components out of the way, to avoice confusion 2023-02-21 16:10:54 +01:00
Jean-Paul Chaput db56681025 More tweaking in the H-Tree Y offset, to avoid stacked VIAs. 2023-02-15 15:17:28 +01:00
Jean-Paul Chaput 07f269196b Manage new cases of stacked VIAs potential creation.
When placing a vertical M1 (and setting it's axis), the perpandiculars
M2 extremities changes, and they have a VIA. If they are already placed
too, they may silently create a stacked VIAs because the track markers
of the perpendiculars are not taken into account. Now, force to rip them
up so the markers will be re-read. If no stacked VIAs has been created,
the segment will be re-put at it's previous place, otherwise it will be
placed on another track.

* New: Track::hasViaMarker(), check if a marker of a Net is under a
    given interval (so we can know we are about to create a VIA stack).
* New: Manipulator::avoidStackedVias(), ripup perpandiculars to the
    current segment that *may* create stacked VIAs. That is perpandicular
    in the *up* layer which begin or end on the moved vertical.
* New: In SegmentFsm::insertInTrack(), bindTotrack() & moveToTrack(),
    call Manipulator::avoidStackedVias(), if activated.
* Change: In NegociateWidow/loadRoutingPads(), no longer exclude clock
    nets. So the TrackMarkers are created for the root net.
2023-02-14 22:35:56 +01:00
Jean-Paul Chaput 77afb7cba4 Quick for H-Tree driver Y offset (account for root & symmetry). 2023-01-23 14:46:30 +01:00
Jean-Paul Chaput f7b2a4f5bb The previous fix for low metal tech, must apply only for them in htree. 2023-01-19 14:54:00 +01:00
Jean-Paul Chaput 38cc00005d Fix missing VIA & bad offset in htree for low metal techs. 2023-01-19 13:57:35 +01:00
Jean-Paul Chaput 96fe367cc0 Fix overlap of non-used RoutinPads in VH,2RL styles.
* New: In KatanaEngine::digitalInit(), when using a "VH,2RL" style,
    protect all RoutingPads of each net, because unlike "2RL+" style,
    the standard cell RoutingPads are not in a "below" layer only
    used inside the cell, but on the V layer. So the area of the RP,
    even if not fully used to connect, must be protected.
* Change: In NegociateOverlapCost(), when computing cost from a fixed
    or blockage, do not set the infinite flag if it's the *same* net.
* New: In KatanaEngine::protectRoutingPads(), add a new "flags" argument
    to pass on whether we want to protect the the RP candidates or just
    the non-used ones.
* Change: In protectRoutingpad(), change the formula (again) to compute
    the berth to give to a fixed segment... Should really try to
    summarize all the case.
* Change: In TrackFixedSegment::getNet(), no longer return the blockage
    net if the real net is tagged as clock.
2023-01-18 23:42:38 +01:00
Jean-Paul Chaput 047bf14921 Wrong computation of the up/down dogleg layer for 2 layers gauges.
* Bug: In Anabatic::AutoHorizontal::_makeDogleg(), the up/down flag
    was incorrectly computed when the RoutingGauge RL where not the
    lower one. This was leading to making doglegs in non-routable
    layers (but present in the gauge for other purposes).
2023-01-18 23:42:17 +01:00
Jean-Paul Chaput 2116e181de Add a breakpoint *before* global routing loading in cumulus/block.py. 2023-01-18 23:20:28 +01:00
Jean-Paul Chaput c7330041fb Remove unmatched DebugSession::close() in RawGCellsUnder. 2023-01-18 15:49:51 +01:00
Jean-Paul Chaput 7598485a4f Allow the BigVia to stack the cuts in some cases. 2023-01-14 22:38:36 +01:00
Jean-Paul Chaput 9df5fc838c Support for non-stacked VIAs in Katana.
* New: In Katana::Configuration, added option:
    "cfg.katana.disableStackedVias" (default to false), so the router
    do not stack VIAs on top of each other.
* Bug: In NegociateWindow::loadRoutingPads(), create TrackMarkers using
    the right depth when the gauge starts with non-routable ones.
* New: In Track::addOverlapCost(), when disableStackedVias is active,
    uses the markers from the below terminals to tag the cost as
    "infinite", so the track *cannot* be used by the marker's net
    owner. Can be refined by checking that we are not at a segment's
    end but will do for now.
2023-01-14 22:35:57 +01:00
Jean-Paul Chaput 7d88b14334 Keep Sphinx variant documentation sources, just in case... 2023-01-14 12:45:08 +01:00
Jean-Paul Chaput 0a69e7d62d Correct broken links in Python Tutorial documentation. 2023-01-14 12:41:06 +01:00
Jean-Paul Chaput 181b2e1080 Re-enable and check the building of I/O ring with pad spacers.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.

* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
    add a vertical strap segment in case the RP is not high enough to
    accomodate the potential offset of the contact.
      In case of gauge with only two routing layers, if the RP
    is vertically accessed, do not put a VIA12 but just a METAL2
    contact (there will be *no* turn).

* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
    going to the pad was shrunk of 3 pitch when *not* in the preferred
    routing direction. Removing it as it creates gaps in some cases.
      This was likely needed for a specific kind of I/O pad so should
    be re-enabled on targeted cases in the future.

* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
    the conflicts when a rail is accessed from both sides overlapping
    on an Y position. That is, from the supply I/O pads *and* from the
    *core* supply lines.
      Formerly, we just didn't connect the core power line, which was
    a mistake potentially leaving power rails unconnected (it it did
    occur on both sides).
      Also checks if the conflict really arise, that is, the power lines
    are both on top or bottom.

* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
    a bottom left corner of abutment box *not* at (0,0). Argh!

* Bug: In cumulus/chip.pads, create the filler pad instances in the
    chip, not in the corona.
2023-01-14 12:39:22 +01:00