Commit Graph

2535 Commits

Author SHA1 Message Date
Jean-Paul Chaput 76d468f6d5 Change in feed & tie managements to fill the empty row spaces.
* Change: In EtesianEngine::_postCreate(), issue a warning if the list of
    feeds is empy (configuration: "cfg.etesian.feedNames").
* New: Add a FeedCeels::getFeedByWidth() method to get feeds by their
    width in DbU::Unit and not only pitches.
* Change: In Placement::Slice::fillHole(), invert the tie filling and
    feeds filling stage. Now we first try to fill the row hole with
    feeds, using the widest first, and if they are not configured or
    too wide, use the tie.
      As the tie *should* also be integrated in the feed list, we may
    suppress altogether the fallback tie filling step. Keep it for now.
* Change: In Placement::slice::createDiodeUnder(), the inserted diode
    *may* be smaller than the feed it replace. So, in this case, add
    a complementary feed to fill the gap.
    NOTE 1: Out of lazyness, we add only *one* complementary filler
            cell. So there *must* be one of a width wich correspond
	    exactly to the difference between the original feed and
	    the diode. Otherwise, gap will remains.
    NOTE 2: With wider feed cells, they may cross the GCell border.
            But we must insert the diode under the GCell, otherwise
	    the global routing will be defective. So, for now, reject
	    feeds that cross the boundary. Must be done more smartly
	    by inserting the diode over the left or right side of
	    the feed.
2021-12-17 15:58:13 +01:00
Jean-Paul Chaput 4ab6888b94 Fix Pin managment on north & east side of the cell abutment box.
* Change: In AnabaticEngine::setupPrerouteds(), take into account the
    number of Pins. Now consider a net containing multiple Pins and, at most,
    one segment as *non-routed".
      This case may specifically happens for nets with pins on the north
    and east side, which are slightly *inside* the abutment box (to be
    seen by the router) and draw with them their *outside* direct
    connection wire.
* Bug: In cumulus/plugins.chip.CoreWire, no longer put the north or
    east side external Pin *exacyly* on the abutment box but *one pitch*
    inside so they are correctly seens by the P&R (must be *inside*
    the area of a GCell).
2021-12-17 15:56:15 +01:00
Jean-Paul Chaput 67ca0997c3 Merge branch 'fix-blif-zero-one' into 'devel'
blif: Improve detection of zero/one net by requiring it to be external

See merge request vlsi-eda/coriolis!12
2021-12-11 21:07:18 +00:00
Jean-Paul Chaput 73296503ad Merge branch 'devel' of gitlab.lip6.fr:vlsi-eda/coriolis into devel 2021-12-11 22:00:10 +01:00
Jean-Paul Chaput fe32916d14 Add support for the SkyWater130 Caravel harness to "core2chip".
It is now possible to automatically nest a core block inside a harness
frame, like we do for an ordinary chip whith I/O pads. The DEF harness
file "user_project_wrapper.def" must be made available though the block
configuration variable:
   conf.cfg.harness.path = './user_project_wrapper.def'
A first small example is given in:
   alliance-check-toolkit/benchs/counter/sky130_c4m
The harness layout is stripped from it's native power grid (but keep
the power ring). I/O pad information in block/configuration is
slightly "bent* to manage pins instead of complete I/O pads.

* Bug: In cumulus/plugins.block.Block.setupAb(), the routingBb was not
    set up when working in chip mode. Now set (to the corona AB).
* Change: In cumulus/plugins.chip.__init__, move there the CoreWire
    class (from chip/pads.py) so it can be shared with the harness
    version of pads.py.
* Change: In cumulus/plugins.chip.powerplane, compute the intersection
    between the vertical supply stripes and the deep horizontal power
    lines in a smarter fashion, so two (or more) vertically contiguous
    BigVias are merged into one (two BigVia side by side where causing
    mimimal spacing distance violation on the cut in Sky130).
2021-12-11 19:52:31 +01:00
Jean-Paul Chaput 2ca9e162ef Allow the detailed routing to be build from non-bottom P&R layers.
* New: In Anabatic::AutoSegment::create(), allow the created segment to
    be in any supported routing layer, and not only the bottom H & V.
    Modifications impact the *two* overload of the function.
* Change: In Anabatic::NetBuilderHV::doRp_AutoContacts(), for punctual
    METAL1, the protection has to be in METAL2. Bump the layer depth
    to correctly use the updated verstion of AutoSegment::create().
* Change: In AnabaticEngine::checkPlacement(), for the Pin, check that
    it's layer is in the routing gauge before anything else.
* New: In Katana::NegociateWindow::createTrackSegment(), if the track
    nearest the segment axis (refTrack) do not exists, call a
    breakpoint just before crashing.
2021-12-11 19:51:24 +01:00
Jean-Paul Chaput ba2a74e35d Tweaked DEF support to load the Caravel harness.
* Bug: In CRL::BlifParser::Model CTOR, forgot to set the direction
    on auto-generated power supply global nets. So they were put
    in "linkage" in the VST files.
* New: In CRL::DefImport, add specific support for the Sky130/Caravel
    harness "user_project_wrapper".Mainly:
    - Do not fuse together "io_in" and "io_out" as a single net as
      they should (according to the DEF). So we can connect separately
      on each of them. We only allow one port for each net, as in VHDL.
2021-12-11 19:48:57 +01:00
Jean-Paul Chaput 2f0bf5456d Added Etesian to the measurment system.
* Bug: In CRL::MeasureSet::toStringHeaders(), check and issue a warning
    if a measure label ends with a "." (dot).
* Change: In CRL::ToolEngine::getMeasure(), return the data measure
    by pointer instead of by reference (easier to manipulate afterwards).
* New: In EtesianEngine::place(), add the placement runtime (under label
    "placeT") to the measure set.
* New: In KatanaEngine::dumpMeasures(), add the Etesian runtime to the
    set of measures.
2021-12-11 19:47:24 +01:00
Jean-Paul Chaput be598c9b96 Update the Python wrapping of Hurricane::Entity.
* New: In Hurricane::PyEntity, export the getBoundingBox() method.
2021-12-11 19:44:20 +01:00
gatecat 3f08b3789f blif: Improve detection of zero/one net by requiring it to be external
Signed-off-by: gatecat <gatecat@ds0.me>
2021-12-10 19:17:03 +00:00
Jean-Paul Chaput f14ef8adc2 Updated PDFs, December 10, 2021 (15:07). 2021-12-10 15:07:58 +01:00
Gabriel Gouvine b4a7d1a6fd Add SUPPORT.rst file 2021-12-09 22:32:02 +01:00
Gabriel Gouvine 4e23dff0dc Update URL in the README 2021-12-09 22:31:58 +01:00
Jean-Paul Chaput f954f69574 Suppress error message when NDA plugins directory does not exists. 2021-11-28 19:40:59 +01:00
Jean-Paul Chaput b1b67d18e6 Add support of vertical power rails made of powmid cells in Block.
* New: In cumulus/plugins.block.congiguration: New PowersConf config
    sub-object to store characteristics of the "powmid_x0" cell.
    The name of the Cell with which to build the vertical power
    rails is given though the cfg parameter:
      "cfg.etesian.cell.power"
* New: In cumulus/plugins.block.spares, add support for creating
    vertical power lines along with the buffers pools of the H-Trees.
    At most, one vertical power rail will be put exactly at the right
    edge of the buffer pool of each leaf QuadTree. We can reduce that
    number, using the parameter:
      "cfg.block.vRailsPeriod = N"
      Which give the ratio to use (one over N QuadTree leaf).
   WARNING: This may not work if the QuadTree is "dented" not in a
            corner but in the *middle* of the side. Needs to be
	    improved and/or checked.
2021-11-28 19:12:59 +01:00
Jean-Paul Chaput df972b7250 Add Diode/Feed flags in Cell. Correct computation of Instance count.
WARNING: We are partially duplicating the informations pertaining
         to the Alliance catalog (stored in the Catalog property)
	 directly into the Cell. This is needed for Flexlib which
	 is not using the Alliance loading mechanim. Ideally the
	 Catalog information should be moved into the Cell.

* New: In Cell, add new state flags Diode, PowerFeed (in addition to
    Pad & Feed).
      Export flags setter/getter to Python. For Flexlib usage.
* Change: In AllianceFramework::getInstancesCount(), correctly skip
    Diode & Feeds based on Cell flags. Those flags must correctly
    be set in the various Flexlib_fix.py scripts.
2021-11-28 19:03:02 +01:00
Jean-Paul Chaput 01224e6a06 Forgot to disable debug in Track::repair() ... 2021-11-26 23:33:05 +01:00
Jean-Paul Chaput d8218d0698 Fix bad computation of gap in Tracks in some special cases.
* Bug: In Track::repair(), when closing a same net gap, the amount the
    "right" segment duSource must be shifted left was incorrectly
    computed in some instances.
      The previous calculation was assuming that the right edge of the
    gap was at the exact same position than the source extension.
    But when there is a non-preferred direction connected to it, this
    is wrong. Now compute the delta accounting for a difference
    between the right edge of the gap and the source extension.
2021-11-26 18:59:46 +01:00
Jean-Paul Chaput 6a3c9d1d54 Set the a default pixel threshold in CRL/etc/commons.display.
NOTE: Due to Python pathes, the NDA.common is *not* seen, even by NDA
      protected configuration. They are using the non-NDA one. No harm
      in that, just need to be known...
2021-11-26 11:32:33 +01:00
Jean-Paul Chaput 7c0f1fcf58 Fairly compute the flat numbers of instances in a design.
* New: In AllianceFramework::getInstancesCount(), add a flag TerminalNetlist
    to stop recursion on "terminal for netlist" instance level. This is to
    avoid counting physical only or non-routed instances inside hard macros,
    like SRAM blocks. This was leading to an overstimation of the "size"
    in number of gates of the routing problem.
* Change: In KatanaEngine CTOR, call for the terminal for netlist number of
    gates...
2021-11-26 11:29:23 +01:00
Jean-Paul Chaput 966a25181f Optimize Cell::getDeeNet() to fix the slow-down in PowerRails.
* New: In DeepNet, add an DeepNet::Uplink property on the HyperNet
    root net Occurrence so we have a direct two-way link between
    the top (flattened net) and the root of the HyperNet.
      Down link is ensured by the Occurrence, up link by the Uplink
    property.
* Change: In Cell::getDeepNet(), now use the DeepNet Uplink property
    instead of looping over *all* top nets. This was the cause of the
    terrific slow down in PowerRails, especially on flatteneds designs.
2021-11-25 10:49:45 +01:00
Jean-Paul Chaput ca499e024c Restore the measurements taking in Anabatic/Katana.
* New: In AnabaticEngine::printMeasures(), re-enable runtime & memory
    footprint in measurements.
* Bug: In Anabatic::AutoSegment CTOR, correct computation of the initial
    number of global segments. We were relying on the "global" flag,
    which is *not* set at this stage. Now compare source and target
    GCells.
* New: In KatanaEngine::runGlobalRouter(), store H-ovE & V-ovE in
    measurements.
* New: In KatanaEngine CTOR, add the number of gates (flattened) to
    the measurments.
* New: In KatanaEngine::runNegociate(), add the number of GCells to
    the measurements.
* Change: In KatanaEngine::printCompletion(), compute the wirelengths
    in either lambdas (symbolic) or *nanometers* (real).
* New: In cumulus/plugins.block.Block, add a setting to request the
    Katana measurements dumping: "cfg.katana.dumpMeasures"
2021-11-24 15:52:56 +01:00
Jean-Paul Chaput 10bd5510da Fix library linking problem for gcc 9 and above (Ubuntu 20/Debian 11).
* Bug: In all CMakeLists.txt, it seems I was doing a worng use of
    target_link_library(). No longer add dependencies to the C++ base
    library but instead either to the Python associated module or
    to the final binaries. This was inderectly causing the linking
    problem related to Python (which was a misdirection).
* Bug: Typo in FindLibexecinfo.cmake, do not use FindLib[E]xecinfo.
* Change: In CRL/ccore/CMakeLists.txt, activate SKIP_AUTOMOC on
    bison/flex generated files.
* Bug: In viewer/PyHApplication, do not delete the C++ object in
    the Python destroy method.
2021-11-22 00:05:48 +01:00
Jean-Paul Chaput 302accfbb1 Update documentation (by mistake, nothing new). 2021-11-21 23:40:40 +01:00
Jean-Paul Chaput c67e326205 Updated PDFs, November 21, 2021 (22:10). 2021-11-21 22:10:34 +01:00
Jean-Paul Chaput 3b971ddf3e Updated PDFs, November 21, 2021 (19:41). 2021-11-21 19:41:13 +01:00
Jean-Paul Chaput 972ed1be20 In Stratus.st_model, make Model derive from object. 2021-11-21 19:37:32 +01:00
Jean-Paul Chaput 5bf80a95d0 In Katana::Configuration::print(), display the _{h,v}TrackReservedMin. 2021-11-21 19:37:06 +01:00
Jean-Paul Chaput 66e7fd648d In ccb.py, update the organization name to "Sorbonne Université". 2021-11-21 19:36:35 +01:00
Jean-Paul Chaput c595a8e73e No longer straight route the root of a H-Tree.
* Change: In cumulus/plugins.block.HTree._rrouteHTree(), make the
    non-routing of the root net the default policy. Straight routing
    can still be activated with the use of Spares.ROUTE_ROOT_NET.
2021-11-16 17:11:00 +01:00
Jean-Paul Chaput 0f636912e0 Support more configuration 1G_xM1_1PinM2.
* Change: In Anabatic::NetBuilder::construct(), add support for up to 5 M1
    terminals in calling _do_1G_xM1_1PinM2(). When inserting diodes on
    long wires, when there is not enough space underneath, they may end
    up gouped at an end.
2021-11-16 00:28:43 +01:00
Jean-Paul Chaput d72ccca88e Fix wrongly exported internal pin to the north side in H-Tree.
* Bug: In cumulus/plugins.block.HTree._rrouteHTree(), on the top level
    H-Tree, draw a wire to the north side of the abutment box *only*
    if the root (usually clock) signal is *external*. It may be that
    it is *internal*, so must be routed as a normal one to the root of
    the tree.
2021-11-14 23:20:33 +01:00
Jean-Paul Chaput 68ae46ef20 Shift the wire connecting to the root of the H-Tree to avoid shorts. 2021-11-13 22:13:16 +01:00
Jean-Paul Chaput fcf6ec97c3 More fixes for the selection & inspector mechanisms.
* Bug: In Common.h, makes the INSPECTOR_PV_SUPPORT to generate a getRecord()
    by *value* instead of *by reference*. Seems the overload resolution
    system has changed and discriminate between them using now the exact
    match.
      This was causing InspectorWidget::setRootoccurrence() to fail, the
    getRecord(Occurrence) not corectly resolved always returning NULL.
* Change: In Occurrence, now use INSPECTOR_PV_SUPPORT (instead of PR).
* Change: In SelectionPopup, added a _cellWidget attribute to be able
    to call setShowSelection() in ::mouseReleaseEvent(), same as for
    SelectCommand.
* Bug: In SelectionWidget::changeSelectionMode(), reset the _updateState
    to ExternalEmit in *all cases* at the end of the function call.
    Failing to do that was another cause for the selection check box
    to desinchronize.
2021-11-09 10:53:56 +01:00
Jean-Paul Chaput f5bfeb3eae Fix auto-scaling of the grid over the displayed area.
* Bug: In CellWidget::drawGrid(), the scaling of grid was never recomputed
    according to the zoom level. So in low zoom, it was too fine and
    hidding everything underneath...
      Now always display between 1 and 10 lines. Lines are put on the
    grid step.
      Makes the grid draw in dotted lines, seems to looks nicer.
2021-11-06 13:41:15 +01:00
Jean-Paul Chaput 95dd4ab8ff Add minimal DEF support to parse the Caravel harness for Sky130.
* New: In CRL::DefImport, the previous version of the parser was designed
    only to read pure netlists, no physical components. Now add features
    for:
    * VIA generate statements. Generated VIAs are created as Cell and
      then instaciated wherever they are needed. Alternative would be
      to duplicate it's contents so the original netlist is not changed.
      But would create lot more objects.
    * PIN, added support for basic physical shapes.
    * SPECIALNETS and their associated wiring (path callback).
    Note: (to myself) As the Path is created *before* the NET or SPECIALNET
          callback is called, we must create a temporary net to store
          the path components. This is the "__prebuild__" net which
          will be merged later with the actual net.
2021-11-06 11:51:39 +01:00
Jean-Paul Chaput 92484ccbb2 Fix bug in the Cadence/DEF parser, occuring on the PathCbk.
* Bug: In def/def_keywords.cpp, in defrData::pathIsDone(), the attribute
    defrData.PathObj was *forcibly* deleted directly inside the defrData
    class (with defrData remaining allocated). Either there is something
    I enterily miss or this is a big blunder.
      This was causing DefImport parser to crash, when activating the
    Path callback.
2021-11-06 11:40:48 +01:00
Jean-Paul Chaput 846ac49ab8 Finally solve the selection desynchronisation problem.
* Bug: In CellViewer::setShowSelection(bool), this slot is connected
    to the hidden 's' menu key. It was toggling state according to
    the state of the *menu key* (Qt) which was *not* kept in synch
    with the state of the CellWidget. So it was causing desinchronized
    selection visibility toggle. Now, ignore the state of the menu
    and toggle the CellWidget state directly.
* Bug: In Selector::attachTo(), when adding the new CellWidget to the
    map<>, the initial flag must be Selector::Selected instead of 0,
    so we see it.
* Change: In CellWidget & ControllerWidget, adjust the default size of
    the widgets (to better suit my display...).
2021-11-03 14:27:21 +01:00
Jean-Paul Chaput 247ddb3a5c Suppress wrong error message in Katana::Session::_addMoveEvent().
* Bug: In Katana::Session::_addMoveEvent(), an error message is issued if
   the segment is not *already* in a Track. But, it is not the case for
   non-preferred Segment or reduced segment and it is valid. So suppress
   the message in those cases.
2021-11-03 14:26:53 +01:00
Jean-Paul Chaput dcc26f23c7 Fix offset track and extension problem in the H-Tree.
* Bug: In cumulus/plugins.block.htree._connectLeaf(), when HEAVY_LEAF_LOAD
    was used, the additionnal horizontal segment added to connect the
    extra buffer may have been:
    1. Misaligned, causing the blockage to be wrongly taken into account
       and leading to potential short circuits.
    2. In some RoutingGauge configurations, the extra length added to
       the segment left extention was too short, leading to DRC violations.
    So created new GaugeConf methods to manage thoses problems:
    * GaugeConf.getStackX() & GaugeConf.getStackY() to get back the
      contact coordinates of the *deep* part (typically the METAL2).
      So be able to align on them.
    * GaugeConf.createHorizontal(), added a parameter to explicitely
      state the additional length of the *left* extension. This is lazy,
      will soon add both.
2021-11-02 10:30:33 +01:00
Jean-Paul Chaput 53f019d165 Merge branch 'const-fix' into 'devel'
Fix 'static assertion failed: comparison object must be invocable as const'

See merge request vlsi-eda/coriolis!9
2021-10-31 11:20:20 +00:00
Myrtle Shah 5b5922096a Fix 'static assertion failed: comparison object must be invocable as const'
Signed-off-by: Myrtle Shah <gatecat@chipflow.io>
2021-10-30 13:50:44 +01:00
Jean-Paul Chaput 1bb5a0ae15 Merge branch 'pr' into 'devel'
Add Nix code

See merge request vlsi-eda/coriolis!8
2021-10-29 15:30:05 +00:00
Jean-Paul Chaput f41875ccdf Try to blindly correct the linking problem of cx2y. 2021-10-29 17:05:44 +02:00
Jean-Paul Chaput 1592e46a3f At last setup a COPYRIGHT.rst and LICENSE.rst files. 2021-10-29 15:03:03 +02:00
Las Safin abfc63558e
nix: Remove unnecessary `ln` from libresoc test 2021-10-26 23:00:13 +00:00
Las Safin 0f66968a9c
nix: add compatibility files 2021-10-26 22:30:34 +00:00
Las Safin 3072c548cd
Ignore /result (from nix-build) 2021-10-26 22:30:33 +00:00
Las Safin fda334e527
nix: Disable tests temporarily 2021-10-26 22:30:29 +00:00
Las Safin b02c387ed5
nix: Remove dependencies on vlsisapd 2021-10-26 21:47:24 +00:00