* Change: In Katana::PowerRailsPlanes::Rail::doLayout(): change the delta
computation. Extend of the pitch *minus* the half wire-width *minus* 1.
So a wire at minimal with will reach exactly the previous and next
track axis. And will not be insterted in them due to the "minus 1".
TrackFixedSegments created at this stage must be flagged as
TElemBlockageNet, so that any overlap between them is not seen as an
error by the track overlap checker.
This was a problem for the clock tree wires which partly uses
pre-fixed wires, but the driver of the H-Tree is a normal signal that
must abide the usual checking.
* Change: In Katana::TrackFixedSegment::getNet(), no longer rely on the
kind of net to choose to return the actual net or the blockage one,
but uses the TElemUseBlockageNet flag.
Formerly, the H-Track could be shifted *relative* to the position of
the center of the RoutingPad. Which may become fragile in case of a
change in the standard cell library. So we create a new feature allowing
to specify the H-track as an offset *from the bottom of the slice*.
Two offset can be specified:
* spares.htreeOffsetDriver : for the main H part, connected to the
driver.
* spares.htreeOffsetSink : for the small parts connecting to every
fours sinks of the tree.
This to avoid those two to overlap. The sink of the "N" stage with
the driver of the "N+1" stage (so input & ouput of the same buffer).
* Change: In cumulus.plugins.core2chip.CoreToChip, add new methods:
* hasCornerCell() (return False)
* hasFillerCells() (return False)
* getCornerCell() (raise NotImplementedError)
* createSpacer() (raise NotImplementedError)
* createCorner() (raise NotImplementedError)
Those methods needs to be overloaded in derived classes when I/O spacers
and corner cells are supplied.
In IoPad, add a NON_CONNECT case for dummy pad that are not connected.
* New: In cumulus.plugins.chip.pads, delegate spacer & corner creation to
the coreToChip concrete class.
* New: In cumulus.plugins.block.configuration.IoPadConf, add support for
non-connected (dummy) pads.
Formerly, CoreToChip was seen as building the top-level netlist of the
chip only. But, when using special spacer pads, we need to have access
to that specific information from inside the Chip pads builder.
So we now move CoreToChip as an internal part of Chip. The right
CoreToChip to use (techno dependant) must be given as a configuration
parameter:
"conf.coreToChipClass"
It is the class, not an object that must be suplied.
* Change: In cumulus.block.configuration and cumulus.block.htree, two new
configuration parameters allow to specify the offset of the horizontal
branch of the H-Tree manually:
cfg.spares.htreeRootOffset (first level of the tree)
cfg.spares.htreeOffset (subsequent levels)
The offset is given in number of tracks.
Formerly we were using Placement::Area::TrackAvoid() to shift cells terminals
out of the way of the reserved vertical track. With double height cells,
this is coming more complex and due to heavy tracks uses in some cells,
the shift required may becomes too great. Instead, we place filler cells
just underneath the reserved track to prevent their usage. This is a
supplemental constraint on the router, but the new version manage it
correctly.
* New: In cumulus/block.spares.Spares.trackAvoid() to place filler cells
under a given vertical area.
* New: In LefImport::LefParser, add support for LEF Polygons that are
translated into Hurricane Rectilinears.
* Change: In LefImport::setMergeLibrary(), the default behavior for the
LEF parser is to create a new separate library under LEF/<lib_name>
for each file. But if the various cells are put each one in it's own
cell, this is suitable. So we can now set a library beforehand into
which they will be all put.
* New: in CRL/technos.node180.gf180mcu, configuration files for the
GF180MCU open PDK.
* New: in cumulus/designflow.technos, added a setupGF180MCU_GF() to
initialize the GF PDK.
* In cumulus.designflow.technos.setupCMOS(): export back the guessed
ALLIANCE_TOP *before* importing technos.symbolic.cmos so it is
used for the CELLS_TOP. This avoid defaulting to /soc/alliance
which does exists only on LIP6 computers...
* New: In cumulus.designflow: add yosysnp to manage Yosys without
Python support enabled.
Add klayout support for running scripts in batch mode.
Add generic system command support.
* Change: In cumulus.designflow.task.TaskFlow, systematically
convert pathes (str) into pathlib.Path in targets and depends.
* New: In cumulus.designflow.clean.Clean, add cleaning by glob.
* Change: In cumulus/plugins/__init__.py, new behavior for loading
plugins supplied as third party. In order to avoid messing up
with the "site-packages/coriolis/" main package tree (with
modules named "coriolis.<MODULE>", they have to be under
"site-packages/addons/coriolis/" (so modules will be named
"addons.coriolis.<MODULE>"). This should prevent *overwritting*
standard modules by third party ones.
Now uses pathlib for module loading.
Had a conflict between Hurricane.Path and pathlib.Path, now do
not import the Hurricane one into the module globals...
* Move all Python stuff under a common Python namespace "coriolis".
* Instead of having a series subtrees for each tool, integrate
everything in one common tree. So now, all components can be
located either with an absolute path from "coriolis" or, inside
cross-reference themselves through relatives imports.
* As a consequence, we only need to add ".../site-packages/coriolis/"
to the PYTHONPATH, and not a whole bunch of subdirectories.
And nothing, if installed in-system.
* The tree of free technologies configuration files is also moved
below "coriolis/technos" instead of "/etc".
* Supressed "cumulus" level for the plugins.
* All python modules are rewritten using relative imports except
for the configuration files that uses absolute import as they
can be cloned outside of the tree to serve as templates.
* Change: In boostrap/FindPythonSitePackages, include "/coriolis" in
Python_CORIOLISARCH and Python_CORIOLISLIB.
Provide a Python_SITELIB *without* "/coriolis" appended.
* Change: In cumulus/plugins/__init__.loadPlugins(), must prefix modules
read in the plugins directory by "coriolis.plugins.". No longer need
to add their path to sys.path.
* Change: In crlcore/python/technos/nodeX/*/devices.py, the scripts of
the layouts generators must be prefixed by "coriolis.oroshi.".
* Change: In CRL::System CTOR, no longer add the pathes of the various
plugins to sys.path. Only "site-packages/coriolis/".
* New: In Utilities::Path::toPyModePath(), new method to convert a
filesystem path into a python module path.
Examples:
"coriolis/plugins/block" --> "coriolis.plugins.block".
"coriolis/plugins/rsave.py" --> "coriolis.plugins.rsave".
* Change: In katanaEngine::_runKatanaEngine(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In BoraEngine::_runBoraEngine(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In UnicornGui::_runUnicornInit(), rename the hook script
initHook.py. No longer need to modify sys.path.
* Change: In cumulus.plugins.chip.constants, put the constants
outside __init__.py to avoid a loop at initialization.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.
* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
add a vertical strap segment in case the RP is not high enough to
accomodate the potential offset of the contact.
In case of gauge with only two routing layers, if the RP
is vertically accessed, do not put a VIA12 but just a METAL2
contact (there will be *no* turn).
* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
going to the pad was shrunk of 3 pitch when *not* in the preferred
routing direction. Removing it as it creates gaps in some cases.
This was likely needed for a specific kind of I/O pad so should
be re-enabled on targeted cases in the future.
* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
the conflicts when a rail is accessed from both sides overlapping
on an Y position. That is, from the supply I/O pads *and* from the
*core* supply lines.
Formerly, we just didn't connect the core power line, which was
a mistake potentially leaving power rails unconnected (it it did
occur on both sides).
Also checks if the conflict really arise, that is, the power lines
are both on top or bottom.
* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
a bottom left corner of abutment box *not* at (0,0). Argh!
* Bug: In cumulus/chip.pads, create the filler pad instances in the
chip, not in the corona.
* Change: In cumulus/plugins.chip.configuration, do not add an extra
slice height to the minHCorona & minVCorona. Now seems a bit overkill
on small chips.
* New: In NetBuilderHybridVH::_do_1G_xM1_1PinM1(), added configuration
to manage pins on the north/south sides for VH,2RL.
* Bug: In NetBuilderHybridVH::doRp_xG_xM1_xM3(), correct misplaced
vertical creation (buildind invalid topologies).
* New: EtesianEngine::toColoquinte(), display histograms of the cells
widths (in pitch) before and after bloating to get a better feeling
of the behavior.
* New: In EtesianEngine, add support for track avoidance. Portions of
tracks to avoid are specified by a Box, which should flat and on
the axis of the request track. This feature is used by the H-Tree
to clear the vertical tracks under the tree from any terminal.
* New: In Etesian::Area, Slice and SubSlice, add support for track
avoidance. Exported to the Python wrapper.
* New: SubSlice::getUsedVTracks() to get a set of tracks blocked by
the cell.
* New: SubSlice::trackAvoid(), shift left/rigth the cell under the
requested vertical track. Try only to move the cell under the
track and not it's neighbor, so it assume that there is sufficient
space left or right of the cell.
* Bug: In cumulus/plugins.block.configuration.BlockConf, the Cfg
parameters may be read too early from the Cfg space into the
various sub-conf objects (like FeedsConf). Delay the reading
of the parameters in a _postInit() functions.
Modify Block and CoreToChip to call _postInit().
* New: In cumulus/plugins.block.configuration.BlockConf._loadRoutingGauge,
allow the cell gauge name to differ from the routing gauge name.
* New: In cumulus/plugins.block.configuration.FeedsConf, allow to
select the default feed to be used with 'etesian.defaultFeed'
parameter.
* New: In cumulus/plugins.block.spares.BufferPool, allow to control
whether or not we want tie to either side of the pool.
(for latch up).
* New: In cumulus/plugins.block.HTree._connectLeaf(), add support
for track avoidance.
* Bug: In cumulus/plugins.block.HTree._connectLeaf(), the TL2 contact,
the one on the *top* auxiliary buffer seemed to have been badly
positioned until now (too low, not using tl2Y).
This is strange because it should have caused disconnections,
but I didn't see it in the wiring and the regressions tests didn't
flag anything wrong. Still a bit weird and worrying.
Previously, the relevant NetBuilder and routing strategies where
directly guessed from the RoutingGauge traits. This is no longer
doable as the combinations increases. Now to configure both the
global and detailed router we need three "parameters" :
1. The routing gauge itself (tells which layers are in which
directions) and how to make the VIAs.
2. The NetBuilder to use, they are identified by strings.
Currently we support:
* "HV,3RL+", for all SxLib derived standard cells.
* "VH,2RL", for hybrid routing (over the cell, but terminals
are also in the first RL).
* "2RL-", for strict channel routing.
* "VH,3RL+", an attempt for FreePDK 45, not optimized enough
to be considered as usable.
3. The routing style, mostly affect the way the GCell grid will be
built.
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
Thoses three parameters are partly overlapping and must be sets in
a consistent manner, otherwise strange results may occurs.
* New: CRL::RoutingGauge::getFirstRoutingGauge(), to get the lowest
layer available for routing (not a PinOnly, not a PowerSupply).
* Change: In CRL::RoutingGauge::isHV() and isVH(), were previously
always returning false when the gauge was 2RL only. Now, check
on the first usable RL.
* Bug: In cumulus/plugins.block.configuration._loadRoutingGauge(),
there was a bad computation of the deep RLs when the top layer
was not defined. Occured for 2RL gauges only.
* Bug: In Anabatic::RpsInRow::slacken() (LayerAssign), forgotten curly braces
in the test to skip METAL2 terminals.
* Change: In Etestian::BloatChannel::getDx(), adjust the bloating
policy to converge on Arlet6502. Always ensure that there is
a 50% ratio between terminal used V-tracks and free ones.
If there is more than 80% of terminals, add one more track.
* Bug: In AnabaticEngine & KatanaEngine, KatanaEngine is a derived
class of AnabaticEngine. They uses Anabatic::Configuration
and Katana::Configuration that also derives from each other.
I though I had made one configuration attribute in the base
class that was using the right Configuration. But no. I did
have two configurations attributes, one in AnabaticEngine and
one in KatanaEngine, the later "shadowing" the former. As a
results, parameters modified in AnabaticEngine, *after* the
initial creation of the tool *where never seen* at Katana
level (due to it's own duplicate). What a mess.
Now there is only one attribute in the *base* class Anabatic,
which is created through a new virtual function _createConfiguration()
called in _postCreate() which allocate the right Configuration
according to the dynamic type of the tool (KatanaEngine).
In KatanaEngine, access the configuration through the
attribute (_configuration) and not the accessor (getConfiguration()).
* Bug: In KatanaEngine, no longer directly use the _configuration attribute
(which is not accessible anyway) but the getConfiguration() accessor.
The accessor perform a static_cast from the Super::getConfiguration()
into Katana::Configuration.
Complete cleanup of the various configuration accessors.
* New: AnabaticEngine::setupNetBuilder(), perform an early check
of the requested NetBuilderStyle. The NetBuilderStyle is just a
string that will be matched against the (hard-coded) supported
NetBuilders. Then check the topological characteristics against
the capabilities of the gauge (HV, VH and so on).
Still a bit too hard-coded for now.
This function has been split from AnabaticEngine::_loadGrByNet().
* Change: AnabaticEngine::isChannelStyle() renamed from isChannelMode().
* New: In Anabatic::Configuration, two new attributes to select the
topology and routing style:
- _netBuilderStyle to explicitely select the NetBuilder to use.
It's a string, which is provided by each NetBuilder.
- _routingStyle to define how the overall routing will work.
It's a set of flags (StyleFlags):
* VH : first RL is V.
* HV : first RL is H.
* OTH : Run in full over-the-cell mode (needs at least 3RL).
* Channel : Run in *strict* channel routing mode (no routing over
the standard cells).
* Hybrid : Create channels, but can use H tracks over the
standard cells.
* New: In anabatic/Constants, add StyleFlags to define how the router
should operate (see above).
* Bug: In Anabatic::GCell, in CTOR, no reason to set up the HChannelGCell flag.
* Bug: In Anabatic::GCell::updateDensity(), when computing layers non contiguous
saturation, do not systematically skip RL 0, but only if it's PinOnly.
* Change: In Anabatic::NetBuilder, rename isTwoMetal by isStrictChannel.
* Change: In Anabatic::NetBuilderHV, rename doRp_AccessNorthPin() in
doRp_AccessNorthSouthPin(). More accurate.
* Bug: In NetBuilderHV::_do_1G_xM1_1PinM2(), the wires to connect the M1
terminals where created *twice*. Uterly stupid, there where placed in
overlap by the router!
* New: In AnabaticEngine, new accessors to the NetBuilderStyle and
RoutingStyle, proxies towards Configuration.
* Bug: In Manipulator::relax(), if there are two doglegs to be done, but
they are in the same GCell, only do one (the conflicting interval)
is short.
* Change: In Katana::Session, rename isChannelMode() into isChannelStyle().
* Change: In TrackSegment::isUnbreakable() and isStrap(), return false
when the base segment is a *weak global* (aligned with a global one).
* Change: In Katana::Row::createChannel(), correctly distinguish between
*strict channel* style and *hybrid* style. Tag the GCells as std cells
row or channels only in the former case.
* New: Hurricane::ErrorWidget, new widget exported to Python to replace
helpers.io.ErrorWidget.
* New: Hurricane::AboutWindow, new window exported to Python to replace
cumulus/plugins.aboutwindow.AboutWidget.
* Change: In cumulus/plugins.sram.sram_256x32, add a new parameter to
__init__() so the user can choose the model name of the generated
SRAM.
* Change: In cumulus/plugins.sram.sram.BaseSRAM.placeInstance(),
placement status must be FIXED instead of PLACED so the placer do
not "unplace" them.
The Cell.updatePlacedFlag() method must also be called once
the model if fully built.
* Change: In CRL/helpers.io, the ErrorWidget requires PyQt5 to execute but
is not mandatory to run Coriolis/cgt. In order to be more portable,
if it is not availble just evert to text display on the console.
This widget will be directly supplied by Coriolis in the future
completely removing the need for PyQt.
*Change: In cumulus/plugins/aboutwindow, same as above.
* New: In cumulus/plugins/sram_256x32.py, build the output mux using a
NAND2/NOR2 binary tree instead of mux2/mux3. Use more, but much
smaller cells. The reduction of wirelength (from Yosys) goes
from 4% to 15% for the non-folded variant.
Uses a specially placed tree to minimize wire length.
* New: In cumulus/plugins/sram.py, extend StdCellConf to convert names
accross library flavors (FlexLib_TSMC_C180, FlexLib_Sky130 and
generic SxLib).
The generator as been build in two parts:
1. A genereric sram.BaseSRAM class to provides support for all kind of
SRAM (grouping column tree, headers, folding).
2. The specific SRAM_256x32 (256 words of 32 bits) suited for the
ethmac.
The sram has been simulated with genpat+asimut and gives identical
results to the Yosys one (at gate level). No timing though.
* Bug: In cumulus/plugins.block.htree.HTree._connectLeaf(), the stacked
contact to connect the top left buffer amplifier was not forcibly
aligned on the vertical METAL5. In some configuaration it was
leading to gaps at METAL5 level.
Jean-Paul Chaput
Gabriel Gouvine