- A complete sweep of cleanup to suppress allmost all compiler warnings.
* ./vlsisapd/openchams:
- Change: Completly remove Name as std::string are shared. Also impact
amsCore (OpenChamsParser/OpenChamsDriver).
* ./vlsisapd/configuration:
- Bug: Python.h must be included first (see Isobar comment).
- Change: New "readFromFile()" Configuration method.
- New: Support for tarball directly from the user checkout (--user-tarball).
- New: Full parametrization through a "build.conf" file.
- Change: Uses user-defined exceptions to terminate.
- New: guessOs() now detect FreeBSD 8.
* ./bootstrap/coriolisEnv.py,
./bootstrap/coriolis2.sh:
- Bug: 'lib64' instead of '64' under Linux.
- New: guessOs() now detect FreeBSD 8.
- Change: Remove support for Coriolis 1. No more --v2 option either, Coriolis2
selected by default. Python paths also set by default.
- Change: In Parameters, suppress the two separate maps, one for double
and another for string (equations). We shouldn't suppose what kind
of data an user can put in the parameter's value. Now that the
parameters for the HB-Tree are to be integrated, we have not only
double but boolean, integers and a direction string. The value are
now stored in a raw fashion as strings. It is up to the parser/drivers
(i.e OpenChamsParser/OpenChamsDriver) to give meaning to those strings
and interpret them accordingly.
- Change: In Circuit, helper templates (and some non-template) functions
to cast a string into various types. All the POD through stringAs<>
template, plus stringAsDirection() & stringAsBool(). Reverse functions
templates asString<> are also avalaible.
Note: Those helpers are of more general interest, we should displace
them sooner or later into a common "Utility" sub-tool.
- Bug: In ./cmake_modules/FindBootstrap.cmake, fix small message display
typos. No 'IN LISTS' in forach call. Force variable lookup in
SEARCH_SETUP_DIR in foreach summarizing the search path.
- Change: In RoutingEvent::State::conflictSolve1_v1b(), when finding obstacles
in candidates tracks, no longer ignore blockages (segments from pads that
connot be broken because they see *no* conflicts...).
- Bug: In placeandroute.py/createGrid(), VIAs of the big clock grid must
have the same width as the wires (12l). But due to the layer extension
the VIA side must be of 11l.
- Bug: In placeandroute.py/createGrid(), wires connecting cell clock pin
to the clock trunk must respect the preferred routing direction.
The only exception being when the wire is completly enclosed under
the trunk wire. This is for the obstacle stage of the detailed router.
- Bug: In ApParser.cpp, the connectors where not parsed. The problem
was not showing if you run all Stratus scripts in the same process
as the caching mechanism will prevent the parsing of the disk file
and uses the memory copy (which is correct).
- remove callOrder member on Operator
- add order on Instance (to order Devices and Subcircuits)
- update python interface
- update C++/Python parse/drive examples