export and simul with standard VHDL
This commit is contained in:
Roselyne Chotin
parent
ab008d2ad9
commit
392accdf27
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@ -54,6 +54,8 @@ from Hurricane import *
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import re, types, string
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import st_config
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FRAMEWORK = None
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EDITOR = None
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@ -87,6 +89,7 @@ class Model :
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self._name = nom
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self._param = param
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self.pat = None
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self._hur_cell = hurCell
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@ -474,13 +477,16 @@ class Model :
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if views == STRATUS :
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self.exportStratus ( fileName )
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else :
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elif st_config.format in ['vst','vhd'] :
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UpdateSession.open()
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hurCell = self._hur_cell
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if str ( hurCell.getName() ) != "__Scratch__" :
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FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical )
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if st_config.format == 'vst' :
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FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical )
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else :
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self.exportVHD()
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if len ( CELLS ) == 0 :
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err = "\n[Stratus ERROR] Save : CELLS stack is empty.\n"
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@ -490,15 +496,48 @@ class Model :
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UpdateSession.close()
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elif st_config.format == 'stratus' :
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self.exportStratus ( fileName )
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elif st_config.format == 'vlog' :
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raise Exception('Format %s not yet implemented' % st_config.format)
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else :
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raise Exception('Unrecognized format %s' % st_config.format)
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##### Simul : in order to use simulation tool #####
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def Simul ( self, name = None, tool = 'asimut' ) :
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from utils import runpat
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if not name : name = self._name
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if tool == 'asimut' : runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' )
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if st_config.simulator == 'asimut' :
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runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' )
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elif st_config.simulator == 'ghdl' :
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import os
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cmd_str = ('ghdl -c -g -Psxlib --ieee=synopsys *.vhd -r %s_run --vcd=%s.vcd' %(name,name))
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os.system(cmd_str)
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elif tool == 'asimut' : runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' )
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else : raise Exception ( 'not implemented yet' )
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##### TestBench : in order to create testbench #####
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def Testbench ( self ) :
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import stimuli
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stim = stimuli.Stimuli(self)
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if st_config.format == 'vhd' :
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# Create stimuli input file
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stim.create_stimuli_text_file()
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# Create testbench
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stim.create_testbench(delay = 20, unit = 'ns', debug = False, downto = True, logic = False)
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# Create testbench and block instance
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stim.create_run(debug = False, downto = True)
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elif st_config.format == 'vst' :
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stim.create_pat_file()
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else :
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raise Exception('Testbench not yet implemented for format %s' % st_config.format)
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##### Create a stratus file given the database #####
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def exportStratus ( self, fileName ) :
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@ -708,6 +747,186 @@ class Model :
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##### End #####
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file.close ()
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##### Create a IEEE VHDL file given the database #####
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def exportVHD ( self ) :
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file = open ( self._name + '.vhd', "w+" )
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file.write ( "--\n" )
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file.write ( "-- Generated by VHDL export\n" )
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file.write ( "--\n" )
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file.write ( "library ieee;\n" )
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file.write ( "use ieee.std_logic_1164.all;\n\n" )
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if 'realModel' in self._param :
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file.write ( "library sxlib;\n" )
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file.write ( "use sxlib.all;\n\n" )
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##### Entity #####
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file.write ( "entity %s is\n" % self._name )
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file.write ( " port(\n" )
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strPorts = ""
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for net in self._st_ports :
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if net._arity == 1 :
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strPorts += " %s : %s std_logic;\n" % ( net._name, net._direct )
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else :
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strPorts += " %s : %s std_logic_vector(%d downto %d);\n" % ( net._name, net._direct, net._arity-1+net._ind, net._ind )
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for ck in self._st_cks :
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if ck._ext:
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strPorts += " %s : IN std_logic;\n" % ( ck._name )
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file.write(strPorts[:-2])
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file.write ( "\n );\n" )
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file.write ( "end %s ;\n\n" % self._name )
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##### Architecture #####
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file.write ( "architecture structural of %s is\n" % self._name )
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# Components
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if 'realModel' in self._param :
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cellList = [self]
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else :
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cellList = self._underCells
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for cell in cellList :
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if 'realModel' in self._param :
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nom = cell._param['realModel']
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else :
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nom = cell._name
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#classe = str(cell.__class__)
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#nom = cell._name
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#param = cell._param
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#print "nom " + nom
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#print "classe " + classe
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## Gestion of libraries with specific treatment
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#chaine = re.search ( "(.*)\.([^\.]*)", classe )
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#if chaine :
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# fichier = chaine.group(1)
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# if re.search ( "dpgen_", fichier ) or re.search ( "st_", fichier ) :
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# classe = chaine.group(2)
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# # Special treatment for virtual library
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# if classe == "Bool" :
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# #nom = cell._name
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# nom = cell._param['realModel']
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# classe = cell._param['model']
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# param = cell._param
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# #del param['model']
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# #del param['realModel']
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#classe = string.upper(classe[0]) + classe[1:] #FIXME !!!
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#if re.search ( "(.*)\.([^\.]*)", classe ) : # ArithLib generator
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# classe = string.lower(classe[0]) + classe[1:]
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file.write ( " component %s\n" % nom )
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file.write ( " port(\n" )
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# Ports
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strPorts = ""
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for net in cell._st_ports :
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if net._arity == 1 :
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strPorts += " %s : %s std_logic;\n" % ( net._name, net._direct )
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else :
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strPorts += " %s : %s std_logic_vector(%d downto %d);\n" % ( net._name, net._direct, net._arity-1+net._ind, net._ind )
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for ck in cell._st_cks :
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if ck._ext:
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strPorts += " %s : IN std_logic;\n" % ( ck._name )
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file.write(strPorts[:-2])
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file.write ( "\n );\n" )
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file.write ( " end component;\n\n")
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# Signals
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for net in self._st_sigs :
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if net._to_merge :
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towrite = False
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for paire in net._to_merge :
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if paire == 0 : towrite = True
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if not towrite : continue
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if net._arity == 1 :
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file.write ( " signal %s : std_logic;\n" % net._name )
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else :
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file.write ( " signal %s : std_logic_vector(%d downto %d);\n" % ( net._name, net._arity-1+net._ind, net._ind ) )
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# Instances
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file.write ( "\nbegin\n" )
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for inst in self._st_insts :
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#chaine = re.search ( "([^_]*)_(.*)", inst._name ) #XTOF FIXME !!!
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#instName = chaine.group(1) #XTOF FIXME !!
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file.write ( " %s : %s\n" % ( inst._name, inst._model ) )
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file.write ( " port map(\n" )
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# Map
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strMap = ""
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for pin in inst._map :
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toto = False
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tata = False
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netInMap = inst._map[pin]
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if netInMap._real_net :
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nom = netInMap._real_net._name
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else :
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nom = netInMap._name
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# <=
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if netInMap._to_merge :
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oneperone = True
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for i in range ( len ( netInMap._to_merge ) ) :
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paire = netInMap._to_merge[i]
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if paire :
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net = paire[0]
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if i > 0 :
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if netInMap._to_merge[i-1] != 0 :
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netbefore = netInMap._to_merge[i-1][0]
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else :
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oneperone = False
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break
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if net != netbefore :
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oneperone = False
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break
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if paire[1] != i :
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oneperone = False
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break
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else :
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toto = True
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oneperone = False
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break
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# "easy" case : 1 per 1 corresponding
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if oneperone :
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netInMap = netInMap._to_merge[0][0]
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nom = netInMap._name
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# else : Cat of the different signals
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else :
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nom = catName ( netInMap, netInMap._to_merge )
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# Cat
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if netInMap._to_cat :
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tata = True
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nom = catName ( netInMap, netInMap._to_cat )
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if toto and tata : print "Attention est ce un cas bien gere ???"
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if netInMap not in self._st_vdds + self._st_vsss :
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if pin == inst._map.keys()[0] : strMap += " %s => %s,\n" % ( pin, nom )
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else : strMap += " %s => %s,\n" % ( pin, nom )
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file.write(strMap[:-2] + '\n')
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file.write ( " );\n\n" )
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##### End #####
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file.write('end structural;')
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file.close ()
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#### Quit : to quit the current cell without saving #####
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def Quit ( self ) :
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