diff --git a/stratus1/src/stratus/st_model.py b/stratus1/src/stratus/st_model.py index 2d57babb..8572cd81 100644 --- a/stratus1/src/stratus/st_model.py +++ b/stratus1/src/stratus/st_model.py @@ -54,6 +54,8 @@ from Hurricane import * import re, types, string +import st_config + FRAMEWORK = None EDITOR = None @@ -87,6 +89,7 @@ class Model : self._name = nom self._param = param + self.pat = None self._hur_cell = hurCell @@ -474,13 +477,16 @@ class Model : if views == STRATUS : self.exportStratus ( fileName ) - else : + elif st_config.format in ['vst','vhd'] : UpdateSession.open() hurCell = self._hur_cell if str ( hurCell.getName() ) != "__Scratch__" : - FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical ) + if st_config.format == 'vst' : + FRAMEWORK.saveCell ( hurCell, views|CRL.Catalog.State.Logical ) + else : + self.exportVHD() if len ( CELLS ) == 0 : err = "\n[Stratus ERROR] Save : CELLS stack is empty.\n" @@ -490,15 +496,48 @@ class Model : UpdateSession.close() + elif st_config.format == 'stratus' : + self.exportStratus ( fileName ) + + elif st_config.format == 'vlog' : + raise Exception('Format %s not yet implemented' % st_config.format) + + else : + raise Exception('Unrecognized format %s' % st_config.format) + ##### Simul : in order to use simulation tool ##### def Simul ( self, name = None, tool = 'asimut' ) : from utils import runpat if not name : name = self._name - if tool == 'asimut' : runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' ) + if st_config.simulator == 'asimut' : + runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' ) + elif st_config.simulator == 'ghdl' : + import os + cmd_str = ('ghdl -c -g -Psxlib --ieee=synopsys *.vhd -r %s_run --vcd=%s.vcd' %(name,name)) + os.system(cmd_str) + elif tool == 'asimut' : runpat ( self._name, name, '-l 1 -p 100 -zerodelay -nocheckdriver -nostrict -bdd -nowarning' ) else : raise Exception ( 'not implemented yet' ) + ##### TestBench : in order to create testbench ##### + def Testbench ( self ) : + import stimuli + stim = stimuli.Stimuli(self) + if st_config.format == 'vhd' : + # Create stimuli input file + stim.create_stimuli_text_file() + + # Create testbench + stim.create_testbench(delay = 20, unit = 'ns', debug = False, downto = True, logic = False) + + # Create testbench and block instance + stim.create_run(debug = False, downto = True) + elif st_config.format == 'vst' : + stim.create_pat_file() + else : + raise Exception('Testbench not yet implemented for format %s' % st_config.format) + ##### Create a stratus file given the database ##### def exportStratus ( self, fileName ) : @@ -708,6 +747,186 @@ class Model : ##### End ##### file.close () + + ##### Create a IEEE VHDL file given the database ##### + def exportVHD ( self ) : + + file = open ( self._name + '.vhd', "w+" ) + + file.write ( "--\n" ) + file.write ( "-- Generated by VHDL export\n" ) + file.write ( "--\n" ) + file.write ( "library ieee;\n" ) + file.write ( "use ieee.std_logic_1164.all;\n\n" ) + + if 'realModel' in self._param : + file.write ( "library sxlib;\n" ) + file.write ( "use sxlib.all;\n\n" ) + + + ##### Entity ##### + file.write ( "entity %s is\n" % self._name ) + file.write ( " port(\n" ) + + strPorts = "" + for net in self._st_ports : + if net._arity == 1 : + strPorts += " %s : %s std_logic;\n" % ( net._name, net._direct ) + else : + strPorts += " %s : %s std_logic_vector(%d downto %d);\n" % ( net._name, net._direct, net._arity-1+net._ind, net._ind ) + + for ck in self._st_cks : + if ck._ext: + strPorts += " %s : IN std_logic;\n" % ( ck._name ) + + file.write(strPorts[:-2]) + file.write ( "\n );\n" ) + file.write ( "end %s ;\n\n" % self._name ) + + ##### Architecture ##### + file.write ( "architecture structural of %s is\n" % self._name ) + + + # Components + if 'realModel' in self._param : + cellList = [self] + else : + cellList = self._underCells + for cell in cellList : + if 'realModel' in self._param : + nom = cell._param['realModel'] + else : + nom = cell._name + #classe = str(cell.__class__) + #nom = cell._name + #param = cell._param + #print "nom " + nom + #print "classe " + classe + + ## Gestion of libraries with specific treatment + #chaine = re.search ( "(.*)\.([^\.]*)", classe ) + #if chaine : + # fichier = chaine.group(1) + # if re.search ( "dpgen_", fichier ) or re.search ( "st_", fichier ) : + # classe = chaine.group(2) + # # Special treatment for virtual library + # if classe == "Bool" : + # #nom = cell._name + # nom = cell._param['realModel'] + # classe = cell._param['model'] + # param = cell._param + # #del param['model'] + # #del param['realModel'] + + #classe = string.upper(classe[0]) + classe[1:] #FIXME !!! + #if re.search ( "(.*)\.([^\.]*)", classe ) : # ArithLib generator + # classe = string.lower(classe[0]) + classe[1:] + + file.write ( " component %s\n" % nom ) + file.write ( " port(\n" ) + + # Ports + strPorts = "" + for net in cell._st_ports : + if net._arity == 1 : + strPorts += " %s : %s std_logic;\n" % ( net._name, net._direct ) + else : + strPorts += " %s : %s std_logic_vector(%d downto %d);\n" % ( net._name, net._direct, net._arity-1+net._ind, net._ind ) + + for ck in cell._st_cks : + if ck._ext: + strPorts += " %s : IN std_logic;\n" % ( ck._name ) + + file.write(strPorts[:-2]) + + file.write ( "\n );\n" ) + file.write ( " end component;\n\n") + + # Signals + for net in self._st_sigs : + if net._to_merge : + towrite = False + for paire in net._to_merge : + if paire == 0 : towrite = True + if not towrite : continue + if net._arity == 1 : + file.write ( " signal %s : std_logic;\n" % net._name ) + else : + file.write ( " signal %s : std_logic_vector(%d downto %d);\n" % ( net._name, net._arity-1+net._ind, net._ind ) ) + + # Instances + file.write ( "\nbegin\n" ) + for inst in self._st_insts : + #chaine = re.search ( "([^_]*)_(.*)", inst._name ) #XTOF FIXME !!! + #instName = chaine.group(1) #XTOF FIXME !! + file.write ( " %s : %s\n" % ( inst._name, inst._model ) ) + file.write ( " port map(\n" ) + + # Map + strMap = "" + for pin in inst._map : + toto = False + tata = False + + netInMap = inst._map[pin] + if netInMap._real_net : + nom = netInMap._real_net._name + else : + nom = netInMap._name + + # <= + if netInMap._to_merge : + oneperone = True + for i in range ( len ( netInMap._to_merge ) ) : + paire = netInMap._to_merge[i] + + if paire : + net = paire[0] + if i > 0 : + if netInMap._to_merge[i-1] != 0 : + netbefore = netInMap._to_merge[i-1][0] + else : + oneperone = False + break + if net != netbefore : + oneperone = False + break + if paire[1] != i : + oneperone = False + break + + else : + toto = True + oneperone = False + break + + # "easy" case : 1 per 1 corresponding + if oneperone : + netInMap = netInMap._to_merge[0][0] + nom = netInMap._name + + # else : Cat of the different signals + else : + nom = catName ( netInMap, netInMap._to_merge ) + + # Cat + if netInMap._to_cat : + tata = True + nom = catName ( netInMap, netInMap._to_cat ) + + if toto and tata : print "Attention est ce un cas bien gere ???" + + if netInMap not in self._st_vdds + self._st_vsss : + if pin == inst._map.keys()[0] : strMap += " %s => %s,\n" % ( pin, nom ) + else : strMap += " %s => %s,\n" % ( pin, nom ) + + file.write(strMap[:-2] + '\n') + file.write ( " );\n\n" ) + + ##### End ##### + file.write('end structural;') + file.close () + #### Quit : to quit the current cell without saving ##### def Quit ( self ) :