* Bug: In CRL::GdsDriver::hasLayout(), a Cell was saved in the GDSII
stream only if it has a layout, but the check was not accurate
enough. In the Arlet6502, the whole core was missing.
Now check for the abscence of Plugs (not unfinished Nets) and
PLACED/FIXED instances.
* Change: In documentation/build.py, more PEP8 & Python 3 future compliance.
Correct copy of the tools HTML docs on my laptop, to have a full
offline copy of the doc.
* New: In documentation/contents/pages/check-toolkit, duplicate the doc
from alliance-check-toolkit README. Seems it has been inadvertently
removed at some point (?). Have to be careful to maintain in synch
with the toolkit.
* Change: <tool>/doc/*/SoC.css, use Roboto fonts when availables.
* Update: Commit the whole pre-generated docs (Doxygen, Pelican).
* Bug: In CRL/GdsStream::toGdsDbu(), when converting a physical number,
in double to a number of GDSII dbu in int32_t, we must not use the
direct cast int32_t(v) because v can be 2.9999999999 which got
simply truncated into 2 while we want 3. So now use the rounding
function std::lrint() and configure it round to the *nearest*
integer.
Note that we don't check that the long returned can correctly
fit into int32_t.
* Change: In CRL::vstDriver(), remove all Vhdl properties after running.
The properties are not updated if the cell (Entity) change, so the
next time it is called, an incomplete or incoherent state was saved
(for example, incomplete "port map"). Removing all properties is
less efficient but works.
* Cleanup: In CRL/helpers/overlay, remove forgotten debug message.
* Change: In CRL/etc/common/etesian.py, use double parameters
instead of percentages to simplify. For space margin and form
factor. This need the rewrite of coriolis2/settings.py in
alliance-check-toolkit.
* Bug: In CRL/helpers/overlay.CachedParameter.cacheRead(), values where
not read *from* the Configuration DB, due to a forgotten "self.".
In CRL/helpers/overlay.CfgCache.__setattr__(), value was simply
never set! Only interval and set of values were manageds!
In CRL/helpers/overlay.CfgCache.__getattr__(), must distinguish
between two access cases, when were are truly accessing a
CachedParameter, return it's *value*. Otherwise, it is a
recursive CfgCache, then return the object.
* New: In CRL::AllianceFramework::wrapLibrary(), can now add in the set
of AllianceLibrary one which is wrapped around another one. All the
cells must be already present and do attempt to save them with
AllianceFramework (AP parser will drive nonsensical datas).
* New: In CRL/helpers.overlay.CfgCache, create a class to fully handle
all the Configuration parameters settings. That is, range and
enumerated values. This way we can fully create them from
the CfgCache instead of merely changing the value of an
existing one.
Examples:
cfg.anabatic.gcell.displayMode = 1
cfg.anabatic.gcell.displayMode = ( ("Boundary", 1), ("Density", 2) )
cfg.katana.hTracksReservedLocal = 4
cfg.katana.hTracksReservedLocal = [ 0, 20 ]
* New: In CRL/helpers/utils.py, create a Python "class decorator".
Works like a decorator but without the need of implementing
the Concrete/Abstract classes structure Design Pattern.
Create proxies in the derived class for the base class
attributes & methods.
* Change: In cumulus/plugins/alpha/block/configuration.py, enrich
the BlockState object to support core2chip parameters. Make it
even more autonomous from the Block class.
* New: In cumulus/plugins/alpha/core2chip, port of the core2chip plugin
and integration with the alphs/block plugin. At "constant features"
as a first. Only ported "cmos", phlib will be later.
Note: Keep the various hfnsX.py as toolboxes for future experiments.
* New: cumulus/plugins/block/hfns3.py, build the trunk of the
net as a RMST. First with the "Iterative One Steiner Point"
(terribly slow above 100 points) then with FLUTE.
For the global routing trunk, must be very cautious to
check that the cluster "graph point" is the one of the
it's buffer RoutingPad so both end up in the same GCell.
* New: cumulus/plugins/block/timing.py, stub for basic
timing computation and conversion between sink and
capacitance. Currently based on the fake 350nm given as
example in SxLib ("man sxlib"...).
* New: In Hurricane::NetRoutingProperty, add and change the meaning
of the following flags:
- ManualGlobalRoute : now means that a global routing *trunk*
is present, made of "gmetalh", "gmetalv" & "gcontact".
- Manualdetailroute : added, get the former meaning of
ManualGlobalRoute, that is, the detailed routing is
already present for this net, but can be changed by the
detailed router. Implies that it respect the Terminal,
HTee & VTee structuration.
* New: Add Anabatic::Diskstra::loadFixedGlobal(), to account
a manually global net into the edges capacities.
* New: In Anabatic::Edges::ripup(), exclude manually global routed
segments from the ripup. Change the segment sorting function
so that thoses segments are put in head of list (considered
as "smaller").
* Change: In AnabaticEngine::setupPreRouteds(), now detect manual
global routed and manual detail routed signals, and tag them
accordingly.
* New: In AnabaticEngine::Configuration & Session, add proxies
for the global routing layers ("gmetalh", "gmetalv", "gcontact").
* New: In Anabatic::Constants, add flags for global fixed and
detail routed nets.
* Change: In KatanaEngine::updateEstimateDensity(), now use int64_t
for flute coordinates.
* New: Add CRL::RoutingGauge::hasLayer(), to know if a layer is
managed by the gauge (comparison by mask).
* New: In CRL::PyAllianceFramework, export getCatalog(), in PyCatalog,
export the getState(name) method and add a PyCatalog_Link().
In PyCatalogState, add PyCatalogState_Link(), cannot use the
macro because of the C++ name resolution operator (Catalog::State).
* New: In Isobar, export the RoutingPads collection to the Python interface.
* New: In Hurricane::Net, export the getRoutingPads() method to the
Python interface (hence the need of the previous export).
* New: Added multiple clock support in H-Tree generation in alpha/block.
* New: In CRL/etc/<NODE>/<TECH>/plugins.py, added three new parameters
for block plugin config:
"block.spareSide" : The size of the minimum side of a buffered area.
(quad-tree leaf).
"spare.buffer" : The model of the cell buffer to be used.
"spare.maxSinks" : max number of sinks on a buffer before issuing
a warning (non-blocking).
* Bug: In Etesian::BloatCell::getAb(), never apply the bloat profile to
fixed cells. In case of buffers from the spare maxtrix it was leading
Coloquinte to detect an overlap of fixed cells, which it do not
support (rightly so).
* Change: In CRL/helpers.Trace, flush stderr before issuing the trace
message to avoid mixing up stdout & stderr (sometimes misleading).
* Change: In CRL/helpers.overlay.CfgCache, no longer display all the
applied setting after a call to apply(). Too verbose.
* Change: In CRL::Environment, regex_t are now pointers instead of values,
this way the "in initialization" flag can be removed (maybe still too
complicated).
* New: In CRL/helpers.overlay.CfgCache, add support for context manager,
so we can progressively remove the use of Configuration. One class
to use in all contexts (immedaite setting or storing a set of
Cfg parameters).
* New: In CRL/helpers/overlay.py, CfgCache class to hold a set of
configuration parameters and apply it on demand. It has a
different behavior than Configuration.
* Bug: In Hurricane/Commons.h, modify the getRecord<>() templates so
that for both vector<Element> and vector<Element*>, the individual
record created for each element are donne with pointers. That is,
for the vector<Element> case, we take a pointer.
As a general policy, except for the POD types, always use pointers
or references to data in the records/inspector. Never uses values
that can call the copy constructor.
Suppress INSPECTOR_PV_SUPPORT() macro, keep only
INSPECTOR_PR_SUPPORT().
Provide value support only for getString<>() template.
This value & copy constructor problem was causing a crash when
trying to inspect Hurricane::AnalogCellExtension.
* New: In Hurricane::Technology, change the API of the PhysicalRule,
now we can only create/get PhysicalRule, but setting the value of
the rule itself must be done on the rule.
Enhance PhysicalRule to provide for stepped rules, non isotropic
and ratio rules.
Merge TwoLayersPhysicalrule in PhysicalRule, much simpler to
suppress the management of derived classes. That means that we
loose a little memory as some fields are mutually exclusive.
Not a problem considering that there will not be so many of thoses
objects.
* New: In CRL/helpers.analogtechno.py, enhanced DTR support for rules
like:
('minSpacing' , 'metal1', ((0.4,20.0), (0.8,1000.0)), Length, 'REF.1')
('minEnclosure', 'metal1', 'cut1', (0.2,0.3) , Length, 'REF.2')
('minDensity' , 'metal1', 0.30 , Unit , 'REF.3')
The DTR parser has been updated, but not the oroshi.dtr Rule
cache for analog components. Given a rule name, the value used
will be the horizontal one of the first step.
* Change: In hurricane/doc/hurricane, re-generate the documentation
with updated support for Technology & PhysicalRule.
* Change: In CRL/helpers/__init__.py, to ensure a complete restart of
the database the __init__.py must be called again, but it's not the
case with reload() (see Python doc). So helpers.resetCoriolis()
must explicitly removes the Coriolis related Python modules from
sys.modules (calling "del sys.modules[moduleName]").
That list of Coriolis Python modules is built by calling
helpers.tagConfModules(), it will tag all modules added to
sys.modules since startup. It will remove (much) more than
Coriolis modules, but that should be ok.
* Change: In CRL/etc/{node*,symbolic}/TECH/__init__.py, add a call to
helpers.tagConfModules() for the techno modules to be erased on
reset.
* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
1. Bad condition for the use of VstUseConcat. Must be used *only*
when there is more than *one* mapped name.
2. Missing case, when there is exactly *one* mapped name, that
means that we have one full width vector to vector assignement.
There may be another weakness here, for the portmap we assumes
that both vector are mapped in the *same* direction (which is
"downto" by our convention).
3. In the "bit by bit mapping case" (every bits of the vector are
differents bits), use the "signal + bit index" name instead of
juste the signal name (i.e. full width).
Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
we can avoid the YOSYS_FLATTEN.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
undefined directions are typed "linkage". This may not be compatible
with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
of the "linkage" type.
* New: In vlsisapd/PyConfiguration, add asDouble() to the Parameter
Python wrapper.
* New: In CRLCore/helpers/overlay, add support for float parameters
in configuratuon.
* Bug: In CRL::VectorPortmap::toVhdlPortMap(), unconnected bits where
correctly checkeds for multi-bits vectors (both ordered and holed),
but not for mono-bits connections (ONE bit of a vector).
* New: In CRL::NamingScheme, add a flag VstNoLowerCase, and its
management it in the Verilog to VHDL converter.
* Change: In CRL::BlifParser::Model::toVhdlModels(), disable the
lowercasing of identifiers. We shouldn't apply Alliance VHDL
subset constraits when reading blif files. So we will see
uppercase identifiers in Coriolis.
* Change: In CRL::VstParser, no longer lowercase identifiers that
are *not* VHDL keywords. Uppercases are legals in VHDL...
* New: In CRL::Catalog::State, add a new flag VstNoLowerCase to
tell if the VST driver should keep the uppercases.
* Change: In CRL::VhdlEntity, add a VstNolowerCase flag to disable
the lowercasing.
* Change: In CRL::vstDriver, lower case the file name if needed.
remove the previously opened filename if it differs from the
lowercased one.
* Change: In UnicornGui CTOR, disable VHDL enforcement for the
Blif parser.
* Change: In CRL::BlifParser, formerly, a zero/one cell was added for
each vss/vdd direct connection, generating a huge flock of cells.
Now only generate one per netlist.
It can be discussed whether to old behavior is more desirable,
it is a compromise between wire and area.
* Change: In CRL::AllianceFramework::getCell(), if the Cell is marked
as TerminalNetlist, then it may be a standard cell. So it's layout
must be loaded. So now, systematically try to load the layout of
netlist terminal cells.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
newly read MACRO (that is Cell) and sets the Logical, Physical,
InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
new Python "importable" format.
Note: in kite.py, all the gauges (Routing & Cells) must be named
"LEF.CoreSite" to please my LEF parser, so it can match the gauge
name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
from the layers in the RoutingGauge and their associated blockages
instead of sweeping through all the basic layers.
Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
* Bug: In CRL::ApParser::_parseInstance(), the instance coordinates where
stored in *static* variables (boo). Making the parser *not* reentrant.
But in _parseInstance(), it can be recursively called through
getCell() when an sub-instance layout was missing.
Also make non-static all other variables in the various parser
function.
* Bug: In CRL::VstParserGrammar & VstParserScanner, when loading the
instances models, we where loading both logical & physical views.
This was causing cases of reentrency of the parser, with reset
of the lexer static dictionary, leading to memory corruption.
Now the identifiers are stored in the YaccState of each
parsed cell and we only recursively call for the logical view.
* Change: In CRL::ApParser::_parseInstance(), recursively load the
physical views as they are no longer loaded by the Vst parser.
* Change: In CRL::AllianceFramework::getCell(), sets the
TerminalNetlist flag from the state (mode 'C' in CATAL) onto
the cell.
* Change: In EtesianEngine::loadLeafcelllayouts(), new functions to
load the layouts of the leaf cells if only the netlist has been
loaded.
* Bug: In CRL::ApDriver::DumpSegments(), reset the direction field to
NULL between iterations so it is recomputed for each component and
not keeping the first one ever guessed.
* Change: In CRL/helpers, cumulus/plugins, oroshi & karakaze,
Move towards more Python PEP8 compliance:
* All indentations sets to 4 spaces (in progress).
* In plugins, remove messages about software collections
and RHEL (too many case could wrongly lead to that).
Instead systematically uses "helpers.io.catch()".
* Put in lowercases all modules names. Note that C++ exported
modules *keep* their Capitalized names (to preserve the
identity with the C++ namespace).
* When making import, use full path.
* Rename the run function from "ScriptMain()" to "scriptMain()".
* Cleanup: In CRL/etc, remove obsoleted configuration files,
the one ending in ".conf". Keep those who have not been ported
to the new style yet.
* New: In Hurricane/src/configuration, first trial at replacing the
C preprocessor macros by C++ templates. Applied first to configuration
from VLSISAPD.
This is unfinished business, just a limited demonstrator for now.
It is installed as a separate Python library "Cfg2" which do not
interact with the rest of Coriiolis.
The end goal is to fully remove boost and merge VLSISAPD useful
components directly inside Hurricane.
* New: In Isobar::PyResistor, manage type RPOLYH and RPOLY2PH.
* Change: In Hurricane::Resistor, rename plate nets from "PIN1" and
"PIN2" into "t1" and "t2" (try to respect uniform naming scheme).
* New: In Karakaze/AnalogDesign.py, support for reading Resistor
parameters.
* New: In Orosshi, ResistorSnake.py imported from Mariam Tlili's work
and associated Resistor.py to make parameter conversion.
Currently we only uses vertical layout for resistors.
Added METAL2 horizontal terminals for resistors.
* Bug: In CRL::ApDriver::DumpSegments(), when saving RoutingPads build
on Pin *not* at the top level (that is, Pin from an instance),
use the pin's orientation to choose the segment type.
* NORTH/SOUTH becomes a Vertical.
* EAST/WEST becomes an Horizontal.
Formerly, the segment direction was guessed only for the bounding
box, leading to segments in incorrect directions leading to DRC
errors (in nmigen/ALU16, net "b(10)").
* Bug: In CRL/symbolic/cmos/technology.py, forgotten import for
WarningMessage.
* Change: In all tools, FindTOOL.cmake, no longer use LIB_SUFFIX to
search for tool libraries but try "lib64/" then "lib/".
* Change: In bootstrap/socInstaller.py, take Debian 10 into account.
* Change: In bootstrap/docker, move from Debian 9 to Debian 10.
Staf Verhaegen
Jean-Paul Chaput