* Bug: In Hurricane/Commons.h, modify the getRecord<>() templates so
that for both vector<Element> and vector<Element*>, the individual
record created for each element are donne with pointers. That is,
for the vector<Element> case, we take a pointer.
As a general policy, except for the POD types, always use pointers
or references to data in the records/inspector. Never uses values
that can call the copy constructor.
Suppress INSPECTOR_PV_SUPPORT() macro, keep only
INSPECTOR_PR_SUPPORT().
Provide value support only for getString<>() template.
This value & copy constructor problem was causing a crash when
trying to inspect Hurricane::AnalogCellExtension.
* New: In Hurricane::Technology, change the API of the PhysicalRule,
now we can only create/get PhysicalRule, but setting the value of
the rule itself must be done on the rule.
Enhance PhysicalRule to provide for stepped rules, non isotropic
and ratio rules.
Merge TwoLayersPhysicalrule in PhysicalRule, much simpler to
suppress the management of derived classes. That means that we
loose a little memory as some fields are mutually exclusive.
Not a problem considering that there will not be so many of thoses
objects.
* New: In CRL/helpers.analogtechno.py, enhanced DTR support for rules
like:
('minSpacing' , 'metal1', ((0.4,20.0), (0.8,1000.0)), Length, 'REF.1')
('minEnclosure', 'metal1', 'cut1', (0.2,0.3) , Length, 'REF.2')
('minDensity' , 'metal1', 0.30 , Unit , 'REF.3')
The DTR parser has been updated, but not the oroshi.dtr Rule
cache for analog components. Given a rule name, the value used
will be the horizontal one of the first step.
* Change: In hurricane/doc/hurricane, re-generate the documentation
with updated support for Technology & PhysicalRule.
* Bug: In EtesianEngine::place(), reset the placement *only* if we are
*not* placing a sub-block *and* the top cell abutment box is empty.
* Bug: In EtesianEngine::place(), set the instance placement status of
all intermediate instances to PLACED, so the AP driver will save
them (we were having partially saved layout when using hierarchical
designs).
* Bug: In EtesianEngine::resetPlacement(), reset the PLACED flag and
the abutment box on the top cell or sub-block to be placed.
* Change: In CRL/helpers/__init__.py, to ensure a complete restart of
the database the __init__.py must be called again, but it's not the
case with reload() (see Python doc). So helpers.resetCoriolis()
must explicitly removes the Coriolis related Python modules from
sys.modules (calling "del sys.modules[moduleName]").
That list of Coriolis Python modules is built by calling
helpers.tagConfModules(), it will tag all modules added to
sys.modules since startup. It will remove (much) more than
Coriolis modules, but that should be ok.
* Change: In CRL/etc/{node*,symbolic}/TECH/__init__.py, add a call to
helpers.tagConfModules() for the techno modules to be erased on
reset.
* New: In Anabatic::NetBuilder, some GCells configurations of Libre-SOC
"test_issuer" (soclayout/experiments9) did have more METAL1 terminals
than was though possible. Just added more entries in the connexity
table for bigger numbers of METAL1. No new configuration was added,
used the already existing ones.
* Bug: In cumulus/plugins/rsave.py, use "Cell.isTerminalNetlist()"
instead of "Cell.isTerminal()" to find the hierarchical stop
points.
If the root cell to be saved is itself a *terminal netlist*
one, save it anyway. The top level *must* be saved regardless to
it's status.
* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
1. Bad condition for the use of VstUseConcat. Must be used *only*
when there is more than *one* mapped name.
2. Missing case, when there is exactly *one* mapped name, that
means that we have one full width vector to vector assignement.
There may be another weakness here, for the portmap we assumes
that both vector are mapped in the *same* direction (which is
"downto" by our convention).
3. In the "bit by bit mapping case" (every bits of the vector are
differents bits), use the "signal + bit index" name instead of
juste the signal name (i.e. full width).
Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
we can avoid the YOSYS_FLATTEN.
* Change: In Vhdl:::Signal::toVhdlPort(), in Alliance VST signal with
undefined directions are typed "linkage". This may not be compatible
with vasy, so allow to replace them by "in".
* New: In CRL::Catalog::State, add a new flag VstNoLinkage to tell if
the VST driver should not use the "linkage" type.
* Change: In Vhdl::Entity, add a VstNoLinkage flag to disable the use
of the "linkage" type.
* Change: In Hurricane::ExceptionWidget,
- Use a QTextLabel instead of a QLabel, make it "look like" a QLabel.
- Always display using text mode. Not HTML (to preserve indentation).
- Make the text of the error message selectable.
- Make it resizable.
* New: In vlsisapd/PyConfiguration, add asDouble() to the Parameter
Python wrapper.
* New: In CRLCore/helpers/overlay, add support for float parameters
in configuratuon.
* Bug: In CRL::VectorPortmap::toVhdlPortMap(), unconnected bits where
correctly checkeds for multi-bits vectors (both ordered and holed),
but not for mono-bits connections (ONE bit of a vector).
* New: In CRL::NamingScheme, add a flag VstNoLowerCase, and its
management it in the Verilog to VHDL converter.
* Change: In CRL::BlifParser::Model::toVhdlModels(), disable the
lowercasing of identifiers. We shouldn't apply Alliance VHDL
subset constraits when reading blif files. So we will see
uppercase identifiers in Coriolis.
* Change: In CRL::VstParser, no longer lowercase identifiers that
are *not* VHDL keywords. Uppercases are legals in VHDL...
* New: In CRL::Catalog::State, add a new flag VstNoLowerCase to
tell if the VST driver should keep the uppercases.
* Change: In CRL::VhdlEntity, add a VstNolowerCase flag to disable
the lowercasing.
* Change: In CRL::vstDriver, lower case the file name if needed.
remove the previously opened filename if it differs from the
lowercased one.
* Change: In UnicornGui CTOR, disable VHDL enforcement for the
Blif parser.
* In cumulus.plugins.matrixplacer.py, BETA plugins for getting back
matrix-like netlists placement. This plugin is configured *ONLY*
for Libre-SOC FU-FU matrix 30x30.
* Change: In CRL::BlifParser, formerly, a zero/one cell was added for
each vss/vdd direct connection, generating a huge flock of cells.
Now only generate one per netlist.
It can be discussed whether to old behavior is more desirable,
it is a compromise between wire and area.
* Change: In CRL::AllianceFramework::getCell(), if the Cell is marked
as TerminalNetlist, then it may be a standard cell. So it's layout
must be loaded. So now, systematically try to load the layout of
netlist terminal cells.
* Bug: In karakaze/AnalogDesign.readParameters(), when asserting the
type of dspec[0], it can either be a type (for analog devices) or
a Cell object (*not* a type). So the issubclass may fails.
Now check first if dspec[0] is an *instance* of Cell.
This is an anisotropy in the type of the first element of
the devicesSpecs table, but suppress one superfluous parameter.
* New: In Analog, new Parameter derived class "StringParameter",
to support strings. Also added to the Python interface.
* New: In Analog::Transistor, added StringParameters for specifying
track positions. They are named "G.t", "S.t", "D.t" and "B.t".
* New: In Oroshi/wip_transistor.py, now read the track positionning
devices parameters.
* New: In Karakaze/AnalogDesign.doDevice(), read an optional 14th
parameter holding the track positions (example in ADC-SAR).
* Bug: In Anabatic::AutoHorizontal & AutoVertical, in getGCells()
method, do not display the "NULL GCell under" error message if the
segment has just been created. It could on a "wrong" axis position
so the line probing method may fail.
* Bug: In AnabaticEngine CTOR, if the "blockagenet" is created there,
do not forget to set it's type to BLOCKAGE (to avoid later warnings).
* Bug: In Anabatic::NetBuilder::_load(), do not display a warning if the
blockage net has no RoutingPads (it *must* not have one).
* Change: In Karakaze/analogdesign/AnalogDesign.readParameters(),
only Transistor and Capacitors where manageds. So when a devices in
the dspec was from another type, it did issue an error.
Now cleanly skip unsupported (yet) devices.
* Bug: In Bora::SlicingNode::clearGlobalRouting(), as we are unrouting the
cell, the flags set up by Katana must be reset. The Cell is no longer
"Terminal" and it's nets are "Un-flattened".
* Bug: In Anabatic::Session::_revalidateTopology(), when iterating over
_segmentInvalidateds, the vector can be modified. If it leads to a
reallocation we end up on invalid iterators (using freed memory so
sometimes with overwritten contents). Now, iterate with an index
which warranty that we get a valid item at each iteration of the
loop. And, of course, the vector is ensured to not shrink...
* Change: In Anabatic::Session::Session(), reserve (pre-allocate) at least
1024 elements for all vectors. Mostly prevent the above bug and
avoid constant reallocation.
* Change: In CRL::LefParser::_macroCbk(), create a Catalog entry for the
newly read MACRO (that is Cell) and sets the Logical, Physical,
InMemory and TerminalNetlist flags.
* Bug: In CRL::LefParser::_siteCbk(), check for NULL cell gauge.
* New: In CRL::AllianceFramework, add setCellGauge(), to set the default
cell gauge. Exported to Python.
* Change: In CRL/etc/common/technology.py, create variables for VIA
layers, so we can modify their properties afterwards.
* New: In CRL/etc/node45/freepdk45, port the configuration files to the
new Python "importable" format.
Note: in kite.py, all the gauges (Routing & Cells) must be named
"LEF.CoreSite" to please my LEF parser, so it can match the gauge
name with the SITE name for standard cells.
* Bug: In Anabatic::NetBuilderVH::_do_2G(), forgotten to be reimplemented
from the base class. Simply redirect to _do_xG().
* Change: In Katana::PowerRailsPlanes::PowerRailsplanes(), create plane
from the layers in the RoutingGauge and their associated blockages
instead of sweeping through all the basic layers.
Allow to distinguish bewteen "METAL" (symbolic) and "metal" (real).
* Bug: In Katana::NegociateWindow::createTrackSegment(), *fixed* AutoSegment
in conflict with blockage where removeds. This was creating "holes"
in the Anabatic articulated segment structure. Now just *don't*
create the TrackSegment. Pass the regression tests, but not sure
it is not generating problems elsewhere.
* New: AnabaticEngine::checkPlacement() to issue more clear errors about
a defective placement.
* Bug: In CRL::ApParser::_parseInstance(), the instance coordinates where
stored in *static* variables (boo). Making the parser *not* reentrant.
But in _parseInstance(), it can be recursively called through
getCell() when an sub-instance layout was missing.
Also make non-static all other variables in the various parser
function.
* New: In Anabatic::NetBuilderHV(), added configurations to manage
one Pin M3 + one M1 terminal plus 2 & 3 globals:
* _do_2G_1M1_1PinM3()
* _do_3G_1M1_1PinM3()
They were occuring for the first time in soclayout/experiment7
in the "flat" approach.
* New: In Katana::runNegociate(), mark the newly routed netlist as
"NetlistTerminal" so it is not placed and routed *again* when
reused as an instance (mostly interract with Etesian).
* Bug: In CRL::VstParserGrammar & VstParserScanner, when loading the
instances models, we where loading both logical & physical views.
This was causing cases of reentrency of the parser, with reset
of the lexer static dictionary, leading to memory corruption.
Now the identifiers are stored in the YaccState of each
parsed cell and we only recursively call for the logical view.
* Change: In CRL::ApParser::_parseInstance(), recursively load the
physical views as they are no longer loaded by the Vst parser.
* Change: In CRL::AllianceFramework::getCell(), sets the
TerminalNetlist flag from the state (mode 'C' in CATAL) onto
the cell.
* Change: In EtesianEngine::loadLeafcelllayouts(), new functions to
load the layouts of the leaf cells if only the netlist has been
loaded.
* Bug: In CRL::ApDriver::DumpSegments(), reset the direction field to
NULL between iterations so it is recomputed for each component and
not keeping the first one ever guessed.
* Bug: In Katana::AutoSegment::_preDestroy(), remove the segment from
the source & target AutoContact cache.
In LibreSOC/experiment7, weird placement caused fixed AutoSegment
overlaping blockage to be deleteds. It seems to have never occured
before (or at least, no ended up in core dump).
* Bug: In Hurricane::NetRoutingState::getSymValue(), outrageously bad
computation of the symmetric coordinate when the value was superior
to the axis... (shame on me).
* Change: In Anabatic::Disjkstra::load(), for symmetrically paired nets,
check that the axis of symmetry is *outside* the searchArea.
Otherwise, the two mirrored areas overlaps and the two nets will
unescapably be on top of each other. Issue a warning but still
continue.
* Change: In Anabatic::Vertex::isRestricted(), allow perpandicular
wire to go through struts or thin (less than one routing pitch)
node. May have to recheck in the future and restrict to struts
only.
* Bug: In Bora::HVSlicingNode::updateSymNetAxis(), rescursive call in
child node was not systematically done (bad curly brace position).
Also checks that symmetries are not empty before accessing the
front element (one less core dump).
* Bug: In Bora/SlicingDataModel, the division was done with integers,
leading so there was a rounding *before* we casted to double.
Now, use the BoxSet::getRatio() method and cast to double *before*
dividing.
* Change: In CRL/helpers, cumulus/plugins, oroshi & karakaze,
Move towards more Python PEP8 compliance:
* All indentations sets to 4 spaces (in progress).
* In plugins, remove messages about software collections
and RHEL (too many case could wrongly lead to that).
Instead systematically uses "helpers.io.catch()".
* Put in lowercases all modules names. Note that C++ exported
modules *keep* their Capitalized names (to preserve the
identity with the C++ namespace).
* When making import, use full path.
* Rename the run function from "ScriptMain()" to "scriptMain()".
* Cleanup: In CRL/etc, remove obsoleted configuration files,
the one ending in ".conf". Keep those who have not been ported
to the new style yet.
* New: In Hurricane/src/configuration, first trial at replacing the
C preprocessor macros by C++ templates. Applied first to configuration
from VLSISAPD.
This is unfinished business, just a limited demonstrator for now.
It is installed as a separate Python library "Cfg2" which do not
interact with the rest of Coriiolis.
The end goal is to fully remove boost and merge VLSISAPD useful
components directly inside Hurricane.
* New: In Isobar::PyResistor, manage type RPOLYH and RPOLY2PH.
* Change: In Hurricane::Resistor, rename plate nets from "PIN1" and
"PIN2" into "t1" and "t2" (try to respect uniform naming scheme).
* New: In Karakaze/AnalogDesign.py, support for reading Resistor
parameters.
* New: In Orosshi, ResistorSnake.py imported from Mariam Tlili's work
and associated Resistor.py to make parameter conversion.
Currently we only uses vertical layout for resistors.
Added METAL2 horizontal terminals for resistors.
* Bug: In CRL::ApDriver::DumpSegments(), when saving RoutingPads build
on Pin *not* at the top level (that is, Pin from an instance),
use the pin's orientation to choose the segment type.
* NORTH/SOUTH becomes a Vertical.
* EAST/WEST becomes an Horizontal.
Formerly, the segment direction was guessed only for the bounding
box, leading to segments in incorrect directions leading to DRC
errors (in nmigen/ALU16, net "b(10)").
* Bug: In CRL/symbolic/cmos/technology.py, forgotten import for
WarningMessage.
* Change: In all tools, FindTOOL.cmake, no longer use LIB_SUFFIX to
search for tool libraries but try "lib64/" then "lib/".
* Change: In bootstrap/socInstaller.py, take Debian 10 into account.
* Change: In bootstrap/docker, move from Debian 9 to Debian 10.
* Change: In bootstrap/coriolisEnv.py, no longer rely on the uname to
choose the library directory (lib64 or lib), but instead look for
those locations (lib64 gets precedence).
* Change: In Hurricane::DbU::setGridPerLambdas(), allow the grid per
lambda to be even. Needed when using nsxlib libraries that are
drawn using a "half lambda" (two lambdas to get an Alliance lambda).
* New: In Oroshi/python, integrated capacitors. Modifications and
correction from Mariam's code:
* No need to redefine __setattr__() on CapacitorUnit.
* Pitch horizontally & vertically (symbolic routing tracks) the
devices.
* Put the horizontal access tracks on the routing pitch.
* Sets the horitontal metal2 wires as external components and
NOT the capacitor plates themselves.
* Makes the size (plates) of the unit capacitor a multiple of
the foundry grid, not a floating number...
* Correct the net ownership of horizontal tracks in
drawHRoutingTracks().
* Simplification & put error management directly inside of
__isCapacitorUnitOK__().
* New: In Karakaze/python/AnalogDesign, capacitor spec now include
the dummy parameter.
Jean-Paul Chaput
Marie-Minerve Louërat