* Change: In Cumulus/plupins.chip.pads.Side, in some case (LibreSOCIOPads),
when not put side by side, the I/O pads must be separated by a
minimal distance.
Introduce the new configuration parameter:
cfg.chip.minPadSpacing
Disabled if zero or non-defined.
Fix NWELL DRC errors for TSMC.
* Change: In AutoSegment::isMiddlestack(), we where previously only
detecting (turn+turn) or (turn+terminal) topologies. This was
too restrictive. Added (terminal+XTee) when the tee is perpandicular
to the segment, for example horizontal + VTee.
Fix minimal area DRC error in METAL2 for TSMC.
* Bug: In Vhdl::VhdlPortmap::toVhdlPortMap(), when the mapped names
are part of a vector, but *not* in the "downto" direction,
unvectorize anyway. In the component declarations, vectors are
always in "downto" order, so they must also be mapped in that
order.
* Bug: In CRL::BlifParser::newOne() & newZero(), we have to create
signal names different from instance names for VHDL compliance.
This is complementary to what is done in blif2vst.
No completely satisfied with that. Should find a more generic
way to do it in the future.
* Change: In Hurricane::NetAlias, store additional data in NetAliasName,
the external status of the former Net. When a Net::merge() is
performed, we must keep track of whether the merged (destroyed)
one was external and keep that information.
Add NetAliasHook::isExternal() & NetAliasHook::setExternal()
virtual methods.
* Change: In Net::getNet() add a new optional argument to allow the
search of the net name in *internal* aliases. Otherwise only the
aliases tagged as *external* will be searched.
It was a bug that, when looking for a Plug master net by name
we got an homonymous internal net. In that case we must only
look for net that are (or where) part of the interface.
* New: In Vhdl::VectorSignal, when a vector contains only one bit,
unvectorize it, like when it is non-contiguous (we use the
isCountiguous() method to carry that information).
* New: In Vhdl::VhdlEntity, Catalog::State and NamingScheme, added
a flag UniquifyUpperCase to uniquify the names in uppercases.
In case of a clash with the same name in lowercase.
Prepend 'u' before all previously uppercased letter. For
example 'VexRiscV' becomes 'uvexuriscuv' (urgh!).
The Catalog flags is exported to Python for use by the blif2vst
script.
* Change: In BlifParser, Model::newOne() and Model::newZero(), return
a new gate each time it is called instead of making just one for
each Model. This way, if two outside nets are connected to one
or zero they do not get merged (should work, but will be less
clear).
* Bug: In BlifParser, Model::connectSubckts(), when looking for the
master net in the instances models (by name), limit the search
to the *external* aliases names.
* Change: In NamingScheme::vlogTovhdl(), reactivate the removal of
two consecutive '_'.
* Change: In cumulus/bin/blif2vst.py, prefix the master cells
(i.e. components) with 'cmpt_' to avoid clash names with signals
in VHDL.
We use the segments extensions (dxTarget & dyTarget) to enlarge if
needed the segments. This new implementation is completely at
Anabatic level and should not be seen (i.e. managed) at Katana level.
* Change: In AutoHorizontal & AutoVertical, change the semantic of
getSourceU() and getTargetU(). formerly they where the end
position of the segment (with extension included), now they
gives the position of the anchor contacts, that is the axis
of the perpandiculars.
* New: AutoSegment::getLength() is still a proxy toward the
Segment::getLength() which returns the length of segment with
dxSource & dxTarget. We introduce a getAnchoredlength()
which returns the length between the centers of the S/T
anchors. That is axis to axis.
This is this length which is now used througout Anabatic.
* New: In AutoSegment::_extentionCaps, add a fourth item to hold
the segment minimal length (to respect minimal area given
the wire width).
* New: In AutoSegment::getExtensionCap(), if the segment has
a non-zero S/T extension, returns it instead of the S/T
contact extension *if it is greated*. The check of the
extension can be disabled by the Flag::NoSegExt flag.
* Change: In AutoSegment::isMiddleStack(), security check on
the presence of source and targets. More accurate detection
of perpandicular in "same layer" with a non-zero length,
So the area is OK, even with a short segment.
* New: AutoSegment::expandToMinLength(), check if a segment is
under the minimal length and expand it if need be by playing
with the dxTarget & dxSource. Tag minimal segments with the
AutoSegment::SegAtMinArea flag. Also try to keep the segment
*inside* it's former (supposedly wider) interval.
* New: AutoSegment::unexpandToMinLength(), to be called on a
formerly minimal sized segment which as grown up. Reset
it's S/T extensions to zero and unset the flag SegAtMinArea.
* Change: In AutoHorizontal::updateOrient(), when the extension
are non-zero, also swap them if needed, to keep the exact
footprint of the segment.
* New: In AutoSegment::revalidate(), check that the segment
respect the minimal length (area), and expand it if needed.
Conversely, if the segment has grown up from a minimal
length state, reset it's extensions to zero.
* Change: In Anabatic::Session::revalidate(), invalidateds
segments are now sorted in such a way that the "middle stack"
ones are revalidateds last. Not recall 100% why...
* New: In Katana::TrackCost, add a computation of the free interval
length we are into (if any). Not used yet, keep it for future
use.
* Change: In KatanaEngine::finalizeLayout(), remove the call to
segments minimum area protection. It is now obsoleted by the
new implementation in Anabatic.
* Change: In Track::check(), call the minimum size/area checker
Track::checkMinArea().
* New: In AutoSegment::getExtensionCap(), when a routing layer has a
minimal area defined, compute the minimal wire length (given it's
width). Then, for segments identified as "MiddleStack" (local
with turns at each end towards opposite layers), if their length
is below minimal, return a longer extention cap.
This may be optimized because with this, the segment extension
is symmetric on both side while it could be made assymetric.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.rpAcces(), start
building the stack of contacts + short segments straps from the
layer of the RoutingPad and *not* from the first layer of the
RoutinhGauge.
* Bug: In Cumulus/plugins.block.configuration.GaugeConf.setStackPosition(),
Only align in the RoutingLayer gauge direction of the top layer of
the stack. For example, METAL2(H) will be y aligned or METAL3(V)
will be x aligned.
* Bug: In Cumulus/plugins.chip.powerplane.Builder._connectClock(),
forgot to call expandMinArea() on the pinRp contact stack.
* Change: In CRL::GdsStream::operator<<(Cell*), external components needs
to be exported twice. First as "METALx.pin" to signal an external
component (and give it's name). And second as a "normal" component
in "METALx". If the METALx part is forgotten, the "Vendor" StreamIn
will not see the METALx.pin as something physical so f***g gaps appears
in the wiring. And furthermore, if the TEXT label is above it, the
name of the net goes away...
* Bug: In EtesianEngine::toHurricane(), when looping over the AB of all the
FIXED instances occurrences, we where excluding contained AB instead of
merging them...
* Change: In Cumulus/plugins.block.spares, allow the QuadTree to have
only *some* of it's four childs (BL, TL, TR, BR).
Modify QuandTree.getLeafUnder() so when there is no leaf under
the point, due to an incomplete tree, we get the closer leaf.
Leaf are suppressed when their center points (where the buffers
are to be put) are under a FIXED Instance (that is, an opaque block).
Those opaque blocks (or macro blocks) must be put *on the periphery*
of the design, because the closer they got to the center, the larger
the chunks of QuadTree that are removeds.
* Change: In Cumulus/plugins.block.clocktree, based on the spare
QuadTree changes, can now build a clock-tree with some of the
leaf missing. Should find a way to compensate for the missing
leaf wires & buffer (dummies).
* New: In Cumulus/plugins.block.matrix.RegisterMatrix, based on pattern
matching the output of DFF, allow to rebuild and place a matrix of
DFF constituting a RAM.
It finally proven not useful because it is a too naive approach.
Intermediate gates (buf_x2) must be found too. Most of the control
signals have more than 20 sinks so gets splitted by HFNS and lastly,
we would want the decoder to be integrated too, but they are not
regulars.
The right way to do it is to create a generator that build it
then expose it in a way nMigen can understand (not the other way
around, nMigen -> Yosys).
* New: CRL::SubNetNames (in ToolBox), takes a VHDL signal name, vectorized
or not and allow to generated sub-net names from it, with respect to
the original vector name.
Examples:
* machin -> machin_hfns_0, machin_hfns_1, ...
* bidule(3) -> bidule_bit3_hfns_0, bidule_bit3_hfns_1, ...
Makes use of the POSIX regex library to avoid Boost dependencies.
* Bug: In HyperNet_ComponentOccurrences::Locator::progress(), (Collection
locator), the _netOccurrenceLocator (which progess along the various
Net occurrences of the HyperNet) was not in synch with the
_componentOccurrence locator of the current net. It was pointing
to the *next* net occurrence.
The result was the generation of a path for the net commponents
that was incorrect (it was the path of the *next* net occurrence),
and making Occurrence constructor throw an exception.
* Change: In Cell::flattenNets(), DeepNet::_createRoutingPads(),
Occurrence::Occurrence() and UpdateSession, added even more trace
informations.
* Bug: In RoutingPad::setExternalComponent(), we where always forcing
the materialization of the RoutingPad (QuadTree insertion). Now
respect the Go::enableAutoMaterialization() state.
Forcing the materialization is equivalent to having an
UpdateSession. So when creating large amount of RoutingPads it did
result in huge slow down, like in HFNS algorithms.
With this modification we go down from 6h+ to 4m for the ls180.
* New: CRL::restoreNetsdirection() (in ToolBox) that checks the coherency
of all Nets direction through a complete hierarchy of cells.
Stops at Cells flagged "TerminalNetlist".
Directions are rebuilt for all the Cells part of the hierarchy
in a bottom up fashion. It is also checked that Nets have only one
driver (we assume there is no three-state busses).
To sort cells in hierarchical order (bottom up according to their
depth), copy the DepthOrder class from the GDSII driver. Will unify
them later.
exported to the Python interface.
* New: In cumulus/tools/blif2vst.py, add a call to restoreNetsdirection()
before saving.
* Change: In NetBuilder::getPositions(), ordering of source/target points
is now integrated to this function instead of left to the caller.
In case of real (non-symbolic) routing gauge, skrink the ends of
half the wire width.
* Change: In NetBuilderHV::doRp_AutoContacts(), in case of non-METAL1
RoutingPad, put the axis of the segment on the nearest track.
Issue a warning if we have to shift, as it may be a potential
source of routing problems.
* New: Anabatic::Session::getNearestTrackaAxis(), proxy to compute
track positions, knowing the design abutment box.
* Bug: In Katana::PreProcess::propagateCagedConstraints(), when
looking at all the slave components anchoreds on a RoutingPad,
if they do not have an AutoSegment lookup, skip them instead
of crashing.
* New: In cumulus/plugins.block.Block.placeMacro(), new method to
place a macro cell, partly delegating to the Macro block wrapper.
Must be called *after* both core and corona abutment boxes have
been set.
Adjust the macro block position so the METAL2 & METAL3 pins
are exactly on pitch regarding the full routing grid. The reference
being the corona.
A shift, less than one pitch may be applied, leading in some
cases of overlapping abutment boxes. But this shouldn't be a
problem.
The macro to place is designated through a path of instances
names, rooted at the *core* (not the corona). Meaning that the
head instance must be one of the core.
* Change: In cumulus/plugins.chip.Chip, the complete chip I/O pads
plus corona and core placement is moved out from doPnR() and
put into doChipFloorplan(). It is now mandatory to call this
method *before* doPnR().
Those methods are now cleanly separated so we can perform macro
block placement or any inner core floorplaning operations between
them.
* Change: In cumulus/plugins.macro.Macro, instead of creating large
pads for the I/O pins so whatever the block position, they will
be under a grid point, create a simple dogleg to put them on
grid.
To ensure that they are "on grid", the block pins must be
in METAL2 (horizontal E/W) or METAL3 (vertical N/S) and the block
is assumed to be placed so the bottom left corner of it's
abutment box is exactly on one grid point for M2/M3.
This should be done by Block.placeMacro().
* New: In KatanaEngine::exportExternalnets(), for commercial tools to
correctly regenerate the external pins from GDSII files it seems
necessary that all segments needs to have TEXT label. So make them
external components.
* Bug: In PowerRailsPlanes::Rail::doLayout(), in case of non-blockage but
fixed segments (that is, power lines), expand the segment box of one
picth to put blockage on too close neigboring tracks.
* Change: In Manipulator::avoidBlockage(), more accurate computation of
the blocked area for pushing aside the terminal & turn of the non-pref
segment.
* New: In cumulus/plugins.chip.powerplane, build the overall power
grid when there is a dedicated supply layer. Makes vertical
supply stripes and connect them the *horizontal* power rails
inside the blocks (could be in *any* layer).
Stripes positions are determined by the pins createds by
the pads module.
* New: In cumulus/plugins.chip.chip, use the powerplane builder
if the RoutingGauge provides a PowerSupply kind.
* New: In cumulus/plugins.block.configuration, add support for
PowerSupply gauges.
* New: In cumulus/plugins.block.pads, if the gauge provides a
PowerSupply, create north/south border pins for power & ground
to direct the corona to make vertical power strips.
This assume that we are using LibreSOC like I/O pads that
can be connected straight from everywhere in the corona.
First and last 2 stripes are "cap end" and narrower.
Positions and width of the sripes are set through the
configuration parameters:
* "chip.supplyRailWidth"
* "chip.supplyRailPitch"
* Change: In cumulus/plugins.block.spares, now take into account
the "placeArea" parameter.
* Change: In cumulus/plugins.block.bigvia, now have a per metal layer
area that *may* be expanded if it is too narrow to put at least
one cut. Add flags to allow controlled expansion of the metal
plates.
As a security, now raise an exception if no cut can be created.
* New: In EtesianEngine::flattenPower(), this is a duplication of the
KatanaEngine::PowerRails. The new paradigm is that when a Cell
is placed by etesian it's AbstractedSupply flag is set and the
creation of the abstract is taken care of at this point.
Should provide some speedup when Katana process it.
Note that we still need to keep PowerRails at Katana stage for
design that are loaded already placed (no Etesian run).
* New: In EtesianEngine::setPlaceArea(), as the slice spin is imposed
on us by Coloquinte, the bottom slice of the place area *must*
be on a ID oriented slice, that is an even one, relative to the
fully placed area.
* Bug: In EtesianEngine, remove the slice spin detection. The spin
is imposed on us by Coloquinte which always place the bottom
row in ID orientation.
Code should be completly removed in the future, along with
the obsolete AddFeeds (replaced by Placement).
* New: In CRL::RoutingLayerGauge, add a new kind of gauge "PowerSupply"
to flag a layer which is dedicated to routing power supplies.
* New: In AllianceFramework, add management of PowerSupply gauge kind.
Exported in the Python interface.
* New: In Query & QueryStack, add a new stop criterion "stopCellFlags"
based on the flags of the instances master cell. The instance will
still be processed, but not it's childs. Typically used to stop
exploring on "AbstractedSupply" cells.
Exported in the Python interface.
* New: In Cell::Flags, new value "AbstractedSupply" to mark Cells from
which an abstract has been built for supplies & blockages. But *not*
for common nets. Helps reduce the recursion through the hierarchy
when building supply line in FlattenPower.
Export setter/getter in the Python interface.
* New: In Instance, add a "PruneMaster" filter to stop hierarchical
exploration on instances which master cells have at least one of
the given flags set.
* Change: In NetExternalcomponents::isInternal(), use "const Component*"
instead of "Component*".
* Bug: In Cell::Flags, the NoFlags must be *zero*, not *one*! And we
can reclaim that bit for future use.
* Cleanup: In Hurricane::Cell, remove changeQuadTree() related methods.
Fusing various Cell's QuadTree is not a viable idea.
* Cleanup: In Hurricane::Instance, remove no longer used "_flags"
attributes.
* New: In cumulus/plugins.macro.macro.Macro() to encapsulate foreign blocks.
Round their size to an exact number of GCells and a guard of one GCell.
External terminal must be on the periphery and will be made to stick out
in the guard ring. This is sub-optimal for now but provide a workaround
some Katana bad assumptions.
A "perpandicular padding" is also added to terminals to limit the
offgrid related problems. Have to optimize that in conjuction with
Katana.
NOTE: To myself, one more bug uncovered in the Track segments management.
This is really too complex, must find time to re-think and simplify
the whole thing.
* New: In Katana::NegociateWidow::createTrackSegment(), detect offgrid
fixed segments and insert them into tracks directly (as *wide* segment
of two tracks).
* New: In Katana::TrackSegment::create() factory method, check for offgrid
fixed segment and use a TrackSegmentWide (of 2 tracks) for them.
* New: In Katana::TrackSegmentWide CTOR, check if they are used in the
context of an offgrid segment and in that case set the track span
to two. We *do not* manage yet the case for both *wide* and *offgrid*
segments.
* Change: In Katana::PowerRails::Rails::doLayout(), do not expand blockage
rectangles over their real size. Add the guard only for real layers
segments.
* Bug: In Katana::PreProcess::propagateCagedConstraints(), when looking
for the first track index, check for out of bound value (npos).
* Bug: In Katana::Track::addOverlapCost(), before using the overlap
segment indexes, check if we are not in a free hole (get the free
interval from center).
* Bug: In Katana::Track::expandFreeInterval(), the interval was badly
computed if it was included inside segments of another (same) net.
* New: In Anabatic::NetBuilder::_do_1G_1M3(), RoutingPad in METAL3 from
blocks are most likely to be offgrid in real mode, we must account
for that case. When an offgrid METAL3 is found, a strap of METAL2
is added, as it may be less than one pitch, it will be reduced into
METAL3 often.
* New: In Anabatic::NetBuilder::doRp_Access(), Support for offgrid METAL2
is added but not enabled yet. Seems to need more polishing.
* Change: In cumulus/plugins.block.Block.__init__(), assume that a block
is already built only if *all* it's instances are placed. Not some
of them.
* New: In cumulus/plugins/block/configuration, added support for a
placeArea parameter to restrict the placement area further than the
abutment box (see Etesian for the new feature).
* Change: In cumulus/plugins/CoreToChip, no longer adds I/O pads for
core signals that lacks one. Only issue an error message and
continue. More useful for debugging block support.
under the fixed segment, we were using the axis *of the segment*,
but if it is very wide, this is completly off.
Now use the axis of the *track* to get the right GCells impacteds.
* Bug: In KatanaEngine::annotateGlobalGraph(), overlapping blockages or
fixed segments where taken into account as separate ones. This was
making the edge capacity reservation too high. Creating false
zero-capacity edges at some points.
Didn't show up until now because we did not have overlaps.
* Bug: In Anabatic::GCell::updateDensity(), the GoStraight flag is now
set in this function when the density of blockage is above 40%.
(should be parametrized in the future). This is linked with the
Katabatic TrackFixedsegment bug.
* Bug: In Anabatic::GCell::Key::Compare, the densities of the GCell
where sorted in the *wrong* order, that is *less denser first*.
This was making the layer assignment working on it's head.
WTF, how did it ever work.
Also sort on global saturation.
* New: In EtesianEngine, add a "placedArea" attribute to restrict the
placement area to a part only of the whole abutement box. This a
way to exclude some area containing *big* hard block.
The placer terribly slow down when tring to "push aside" cells
from the area taken by the block.
This will be also used to restrict the clock tree covered area.
It is far from optimal but will do for now.
NOTE: The placeArea must be expressed in the coordinate system of
the sub-block to be placed, if one has been defined.
* Change: In Model::connectSubckts(), when trying to lookup the
Hurricane Net from it's Blif name, try first as a VHDL one then
after a Verilog to VHDL translation. Especially useful for bits
of vectorized names ("signal[X]" --> "signal(X)").
Jean-Paul Chaput