Commit Graph

2683 Commits

Author SHA1 Message Date
Robert Taylor 4da93f3394 Split out python versions in CI 2023-01-19 16:04:18 +00:00
Robert Taylor b2bbaead53 Pass in python library path to cmake 2023-01-19 16:04:18 +00:00
Robert Taylor 56aa1b189c Use target_link_libraries correctly everywhere to avoid runtime link issues 2023-01-19 16:04:17 +00:00
Robert Taylor deaff0842f fix rpaths - really didn't need quoting 2023-01-19 16:04:17 +00:00
Robert Taylor 90c478e8c4 Update poetry lock 2023-01-19 16:04:17 +00:00
Robert Taylor 4b7973ac84 Fix runtime linking error 2023-01-19 16:04:17 +00:00
Robert Taylor 8ccd9618dd RPATH for libraries to find other coriolis libs 2023-01-19 16:04:17 +00:00
Robert Taylor c1fdf4963b Fixes for cibuildwheel building 2023-01-19 16:04:17 +00:00
Robert Taylor 842602cdcb Support older qwt 2023-01-19 16:04:17 +00:00
Robert Taylor e72c2b7af1 update poetry lock 2023-01-19 16:04:17 +00:00
Robert Taylor b638f235a7 Use the running python for cmake 2023-01-19 16:04:17 +00:00
Robert Taylor f3186d7ed1 try dropping python dependancy and see what breaks 2023-01-19 16:04:17 +00:00
Robert Taylor 06dfdfb52f Add gitlab CI using cibuildwheel 2023-01-19 16:04:17 +00:00
Robert Taylor 198d5ce035 Fix tutorial for python 3 2023-01-19 16:04:17 +00:00
Robert Taylor 449ee2e81e Fix up rpath of binaries 2023-01-19 16:04:17 +00:00
Robert Taylor f604351fa2 Move into Corilois namespace 2023-01-19 16:04:17 +00:00
Robert Taylor 546dfa2f20 Add version and author to pyproject.toml 2023-01-19 16:04:17 +00:00
Robert Taylor c0054eb267 Fix errors when building clean 2023-01-19 16:04:17 +00:00
Robert Taylor 46acf17e47 install helpers at top level 2023-01-19 16:04:17 +00:00
Robert Taylor a0b307b3b4 Add bin files as scripts 2023-01-19 16:04:17 +00:00
Robert Taylor cd4f8560ca Fix Python linking issues 2023-01-19 16:04:17 +00:00
Robert Taylor 8dfd522b71 Give same import semantics for now, fix rpath issue 2023-01-19 16:04:17 +00:00
Robert Taylor d31c489e33 Add Coriolis dir that poetry needs, along with base __init__.py 2023-01-19 16:04:17 +00:00
Robert Taylor 80e83d42ed Poetry package build working for most of coriolis 2023-01-19 16:04:17 +00:00
Robert Taylor 57ac01b54a Move to packaging requiring no changes to CMake 2023-01-19 16:04:17 +00:00
Robert Taylor c277d9f121 Initial Poetry infrastructure 2023-01-19 16:04:17 +00:00
Robert Taylor c41b92e45f Move decprecated components out of the way, to avoice confusion 2023-01-19 16:04:17 +00:00
Jean-Paul Chaput f7b2a4f5bb The previous fix for low metal tech, must apply only for them in htree. 2023-01-19 14:54:00 +01:00
Jean-Paul Chaput 38cc00005d Fix missing VIA & bad offset in htree for low metal techs. 2023-01-19 13:57:35 +01:00
Jean-Paul Chaput 96fe367cc0 Fix overlap of non-used RoutinPads in VH,2RL styles.
* New: In KatanaEngine::digitalInit(), when using a "VH,2RL" style,
    protect all RoutingPads of each net, because unlike "2RL+" style,
    the standard cell RoutingPads are not in a "below" layer only
    used inside the cell, but on the V layer. So the area of the RP,
    even if not fully used to connect, must be protected.
* Change: In NegociateOverlapCost(), when computing cost from a fixed
    or blockage, do not set the infinite flag if it's the *same* net.
* New: In KatanaEngine::protectRoutingPads(), add a new "flags" argument
    to pass on whether we want to protect the the RP candidates or just
    the non-used ones.
* Change: In protectRoutingpad(), change the formula (again) to compute
    the berth to give to a fixed segment... Should really try to
    summarize all the case.
* Change: In TrackFixedSegment::getNet(), no longer return the blockage
    net if the real net is tagged as clock.
2023-01-18 23:42:38 +01:00
Jean-Paul Chaput 047bf14921 Wrong computation of the up/down dogleg layer for 2 layers gauges.
* Bug: In Anabatic::AutoHorizontal::_makeDogleg(), the up/down flag
    was incorrectly computed when the RoutingGauge RL where not the
    lower one. This was leading to making doglegs in non-routable
    layers (but present in the gauge for other purposes).
2023-01-18 23:42:17 +01:00
Jean-Paul Chaput 2116e181de Add a breakpoint *before* global routing loading in cumulus/block.py. 2023-01-18 23:20:28 +01:00
Jean-Paul Chaput c7330041fb Remove unmatched DebugSession::close() in RawGCellsUnder. 2023-01-18 15:49:51 +01:00
Jean-Paul Chaput 7598485a4f Allow the BigVia to stack the cuts in some cases. 2023-01-14 22:38:36 +01:00
Jean-Paul Chaput 9df5fc838c Support for non-stacked VIAs in Katana.
* New: In Katana::Configuration, added option:
    "cfg.katana.disableStackedVias" (default to false), so the router
    do not stack VIAs on top of each other.
* Bug: In NegociateWindow::loadRoutingPads(), create TrackMarkers using
    the right depth when the gauge starts with non-routable ones.
* New: In Track::addOverlapCost(), when disableStackedVias is active,
    uses the markers from the below terminals to tag the cost as
    "infinite", so the track *cannot* be used by the marker's net
    owner. Can be refined by checking that we are not at a segment's
    end but will do for now.
2023-01-14 22:35:57 +01:00
Jean-Paul Chaput 7d88b14334 Keep Sphinx variant documentation sources, just in case... 2023-01-14 12:45:08 +01:00
Jean-Paul Chaput 0a69e7d62d Correct broken links in Python Tutorial documentation. 2023-01-14 12:41:06 +01:00
Jean-Paul Chaput 181b2e1080 Re-enable and check the building of I/O ring with pad spacers.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.

* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
    add a vertical strap segment in case the RP is not high enough to
    accomodate the potential offset of the contact.
      In case of gauge with only two routing layers, if the RP
    is vertically accessed, do not put a VIA12 but just a METAL2
    contact (there will be *no* turn).

* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
    going to the pad was shrunk of 3 pitch when *not* in the preferred
    routing direction. Removing it as it creates gaps in some cases.
      This was likely needed for a specific kind of I/O pad so should
    be re-enabled on targeted cases in the future.

* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
    the conflicts when a rail is accessed from both sides overlapping
    on an Y position. That is, from the supply I/O pads *and* from the
    *core* supply lines.
      Formerly, we just didn't connect the core power line, which was
    a mistake potentially leaving power rails unconnected (it it did
    occur on both sides).
      Also checks if the conflict really arise, that is, the power lines
    are both on top or bottom.

* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
    a bottom left corner of abutment box *not* at (0,0). Argh!

* Bug: In cumulus/chip.pads, create the filler pad instances in the
    chip, not in the corona.
2023-01-14 12:39:22 +01:00
Jean-Paul Chaput 0e17b91692 Add at least one pitch to each cell in BloatChannel profile.
* Change: In Etesian::BloatChannel, when two DFFs are side by side, if
    they are not separated by at least one pitch, the track avoid
    mechanism will not be able to work. Hence the minimal one pitch.
2023-01-14 12:09:43 +01:00
Jean-Paul Chaput 83ff59817a Export CellViewer::setPixelThreshold() to the Python interface. 2023-01-14 12:06:15 +01:00
Jean-Paul Chaput c86d074f06 Export Contact::setLayer() to the Python interface. 2023-01-14 12:05:51 +01:00
Jean-Paul Chaput 3e921ff07a More debug information in chip pad & corona generation.
* Change: In cumulus/plugins.chip.configuration, do not add an extra
    slice height to the minHCorona & minVCorona. Now seems a bit overkill
    on small chips.
2023-01-09 09:26:44 +01:00
Jean-Paul Chaput bdb0091043 Just a little indentation for my autistic self. 2023-01-09 09:21:56 +01:00
Jean-Paul Chaput e38e3f46f2 Route ring pad wires, even if there is no pad on that side. 2023-01-07 13:08:10 +01:00
Jean-Paul Chaput 0bc7b3203a Add DesignFlow to the doc generation. New snapshot of the doc. 2023-01-07 13:01:23 +01:00
Jean-Paul Chaput 30afe6036b Add management of unused layers in cumulus/plugins.block.configuration. 2023-01-07 12:57:23 +01:00
Jean-Paul Chaput d9ebeb4b96 Search path reordering in crlenv.py so the debug version can be found. 2023-01-07 12:53:11 +01:00
Jean-Paul Chaput d2b40d568b Extend routing gauge to support non-routing layers at the bottom.
* New: In CRL::RoutingLayerGauge, two new types of gauge are supported:
    - Unusable : just do nothing with it, but the layer is stacked.
    - BottomPowersupply : can be used for supply routing only, and
      is *below* the normal routing layers (instead of on top as
      usual).
    Both new types must be *below* the real routing layers.
* New: In CRL::RoutingGauge, add a new attribute "firstRoutingLayer"
    to give the index (depth) of the first layer usable for routing.
    (not Unusable and not BottomPowerSupply)
* New: In Anabatic::Session & Anabatic::NetBuilder, in order to build
    the initial wiring, provides (Session) and use (NetBuilder) the
    new functions:
      - getBuildRoutingLayer(depth)
      - getBuildContactLayer(depth)
      Thoses functions takes into account (offset) the unusable layers
    so depth 0 is the first usable routing layer, and so on.
2023-01-07 12:51:38 +01:00
Jean-Paul Chaput 2501688dd1 Add support for layers alias names. Bug in _addPhysicalrule().
* New: In Technology, in order to support symbolic technology on top
    of a real technology using non-generic layer names, it comes in
    handy to be able to define layer alias names. Generic *real*
    layer names could be defined as alias over the technology
    specific ones. Then, we can build the symbolic layers upon
    the generic names (so *that* part of the init code can be
    shared between techs).
       Adds Technology::addLayerAlias()
       The semantic of Technology::getLayer() changes a little, it
     return the techno layer associtated to the name *or* the
     aliased name.
* Bug: In Technology::_addPhysicalRule(), in case of a rule redefinition,
    we were using it's name *after* the deletion of the rule object.
    Nasty crash.
      Improve the error message by giving the name of the conflicting
    rule.
* In CRL/helpers.analogtechno, add an addDevice() function to load
    analogic devices descriptors (copied from the old init system).
* In CRL/ApParser, if an exception is catched, tells in which file and
    line it did occur.
* In Oroshi/dtr.Rules, add a translation step to get the rule names
    from the technology. From generic names to actual technology
    layer names.
       Add some documentation.
* In Oroshi/stack.Stack, get the layers names through dtr.Rules to get
    the layers names translated.
2023-01-05 16:58:49 +01:00
Jean-Paul Chaput da56189d2e allianceInstaller.sh also must support nightly builds. 2023-01-02 12:24:19 +01:00