* Change: In Katana::PowerRailsPlanes::Rail::doLayout(): change the delta
computation. Extend of the pitch *minus* the half wire-width *minus* 1.
So a wire at minimal with will reach exactly the previous and next
track axis. And will not be insterted in them due to the "minus 1".
TrackFixedSegments created at this stage must be flagged as
TElemBlockageNet, so that any overlap between them is not seen as an
error by the track overlap checker.
This was a problem for the clock tree wires which partly uses
pre-fixed wires, but the driver of the H-Tree is a normal signal that
must abide the usual checking.
* Change: In Katana::TrackFixedSegment::getNet(), no longer rely on the
kind of net to choose to return the actual net or the blockage one,
but uses the TElemUseBlockageNet flag.
Formerly, the H-Track could be shifted *relative* to the position of
the center of the RoutingPad. Which may become fragile in case of a
change in the standard cell library. So we create a new feature allowing
to specify the H-track as an offset *from the bottom of the slice*.
Two offset can be specified:
* spares.htreeOffsetDriver : for the main H part, connected to the
driver.
* spares.htreeOffsetSink : for the small parts connecting to every
fours sinks of the tree.
This to avoid those two to overlap. The sink of the "N" stage with
the driver of the "N+1" stage (so input & ouput of the same buffer).
* Switch back to a generated version of the documentation.
Dependencies for the documentation generation have been added to poetry.
As Pelican is a Python tool, that makes sense.
Note to myself: To generate the doc with ccb.py we *need* to be inside
the Python virtual env generated by Poetry. Instead of
relying of a default one, provide one of our own
(coriolis-venv) and make poetry run in it.
* Top builder.py now generated the doc.
* Forgot to remove generated PDFs in the documentation.
* A bit of cleanup on the README.rst
* Forgot the logo. Try to use code-block directive in README.
* Still typo in the logo path.
* One more trial at setting the image position.
* OK. That's enough for the logo.
* Problems with code-block.
* Voila!
* Build inside a venv and use poetry in the top level Makefile.
* Remove doxygen generated docs.
* More doc cleanup in oroshi.
* Change: In cumulus.plugins.core2chip.CoreToChip, add new methods:
* hasCornerCell() (return False)
* hasFillerCells() (return False)
* getCornerCell() (raise NotImplementedError)
* createSpacer() (raise NotImplementedError)
* createCorner() (raise NotImplementedError)
Those methods needs to be overloaded in derived classes when I/O spacers
and corner cells are supplied.
In IoPad, add a NON_CONNECT case for dummy pad that are not connected.
* New: In cumulus.plugins.chip.pads, delegate spacer & corner creation to
the coreToChip concrete class.
* New: In cumulus.plugins.block.configuration.IoPadConf, add support for
non-connected (dummy) pads.
Robert Taylor
Jean-Paul Chaput
Gabriel Gouvine
Rob Taylor