When placing a vertical M1 (and setting it's axis), the perpandiculars
M2 extremities changes, and they have a VIA. If they are already placed
too, they may silently create a stacked VIAs because the track markers
of the perpendiculars are not taken into account. Now, force to rip them
up so the markers will be re-read. If no stacked VIAs has been created,
the segment will be re-put at it's previous place, otherwise it will be
placed on another track.
* New: Track::hasViaMarker(), check if a marker of a Net is under a
given interval (so we can know we are about to create a VIA stack).
* New: Manipulator::avoidStackedVias(), ripup perpandiculars to the
current segment that *may* create stacked VIAs. That is perpandicular
in the *up* layer which begin or end on the moved vertical.
* New: In SegmentFsm::insertInTrack(), bindTotrack() & moveToTrack(),
call Manipulator::avoidStackedVias(), if activated.
* Change: In NegociateWidow/loadRoutingPads(), no longer exclude clock
nets. So the TrackMarkers are created for the root net.
* New: In KatanaEngine::digitalInit(), when using a "VH,2RL" style,
protect all RoutingPads of each net, because unlike "2RL+" style,
the standard cell RoutingPads are not in a "below" layer only
used inside the cell, but on the V layer. So the area of the RP,
even if not fully used to connect, must be protected.
* Change: In NegociateOverlapCost(), when computing cost from a fixed
or blockage, do not set the infinite flag if it's the *same* net.
* New: In KatanaEngine::protectRoutingPads(), add a new "flags" argument
to pass on whether we want to protect the the RP candidates or just
the non-used ones.
* Change: In protectRoutingpad(), change the formula (again) to compute
the berth to give to a fixed segment... Should really try to
summarize all the case.
* Change: In TrackFixedSegment::getNet(), no longer return the blockage
net if the real net is tagged as clock.
* Bug: In Anabatic::AutoHorizontal::_makeDogleg(), the up/down flag
was incorrectly computed when the RoutingGauge RL where not the
lower one. This was leading to making doglegs in non-routable
layers (but present in the gauge for other purposes).
* New: In Katana::Configuration, added option:
"cfg.katana.disableStackedVias" (default to false), so the router
do not stack VIAs on top of each other.
* Bug: In NegociateWindow::loadRoutingPads(), create TrackMarkers using
the right depth when the gauge starts with non-routable ones.
* New: In Track::addOverlapCost(), when disableStackedVias is active,
uses the markers from the below terminals to tag the cost as
"infinite", so the track *cannot* be used by the marker's net
owner. Can be refined by checking that we are not at a segment's
end but will do for now.
* New: In cumulus/block.bigvia, add a getBoundingBox() method.
* New: In cumulus/block.configuration.GaugeConf.rpAccess(),
add a vertical strap segment in case the RP is not high enough to
accomodate the potential offset of the contact.
In case of gauge with only two routing layers, if the RP
is vertically accessed, do not put a VIA12 but just a METAL2
contact (there will be *no* turn).
* Change: In cumulus/chip.CoreWire.drawWire(), the wire at *chip level*
going to the pad was shrunk of 3 pitch when *not* in the preferred
routing direction. Removing it as it creates gaps in some cases.
This was likely needed for a specific kind of I/O pad so should
be re-enabled on targeted cases in the future.
* Change: In cumulus/chip.corona.VerticalRail, manage in a smarter way
the conflicts when a rail is accessed from both sides overlapping
on an Y position. That is, from the supply I/O pads *and* from the
*core* supply lines.
Formerly, we just didn't connect the core power line, which was
a mistake potentially leaving power rails unconnected (it it did
occur on both sides).
Also checks if the conflict really arise, that is, the power lines
are both on top or bottom.
* Change: In cumulus/chip.pads.Side._placePad(), manage I/O pads with
a bottom left corner of abutment box *not* at (0,0). Argh!
* Bug: In cumulus/chip.pads, create the filler pad instances in the
chip, not in the corona.
* Change: In Etesian::BloatChannel, when two DFFs are side by side, if
they are not separated by at least one pitch, the track avoid
mechanism will not be able to work. Hence the minimal one pitch.
* Change: In cumulus/plugins.chip.configuration, do not add an extra
slice height to the minHCorona & minVCorona. Now seems a bit overkill
on small chips.
* New: In CRL::RoutingLayerGauge, two new types of gauge are supported:
- Unusable : just do nothing with it, but the layer is stacked.
- BottomPowersupply : can be used for supply routing only, and
is *below* the normal routing layers (instead of on top as
usual).
Both new types must be *below* the real routing layers.
* New: In CRL::RoutingGauge, add a new attribute "firstRoutingLayer"
to give the index (depth) of the first layer usable for routing.
(not Unusable and not BottomPowerSupply)
* New: In Anabatic::Session & Anabatic::NetBuilder, in order to build
the initial wiring, provides (Session) and use (NetBuilder) the
new functions:
- getBuildRoutingLayer(depth)
- getBuildContactLayer(depth)
Thoses functions takes into account (offset) the unusable layers
so depth 0 is the first usable routing layer, and so on.
* New: In Technology, in order to support symbolic technology on top
of a real technology using non-generic layer names, it comes in
handy to be able to define layer alias names. Generic *real*
layer names could be defined as alias over the technology
specific ones. Then, we can build the symbolic layers upon
the generic names (so *that* part of the init code can be
shared between techs).
Adds Technology::addLayerAlias()
The semantic of Technology::getLayer() changes a little, it
return the techno layer associtated to the name *or* the
aliased name.
* Bug: In Technology::_addPhysicalRule(), in case of a rule redefinition,
we were using it's name *after* the deletion of the rule object.
Nasty crash.
Improve the error message by giving the name of the conflicting
rule.
* In CRL/helpers.analogtechno, add an addDevice() function to load
analogic devices descriptors (copied from the old init system).
* In CRL/ApParser, if an exception is catched, tells in which file and
line it did occur.
* In Oroshi/dtr.Rules, add a translation step to get the rule names
from the technology. From generic names to actual technology
layer names.
Add some documentation.
* In Oroshi/stack.Stack, get the layers names through dtr.Rules to get
the layers names translated.
Robert Taylor
Jean-Paul Chaput