* Change: In Hurricane::Viewer::ExceptionWidget & CRL/python/helpers/io.py,
downscale icons for non-HiDPI screen.
* Change: In CRL/etc/common/display.py, change the display threshold of
METAL1 layer so it do not appear at high scaling.
* New: In Etesian, activate the "setFixedAbHeight()" feature and export it
to Python. Allows to increase the space margin at constant height.
To be used by the P&R conductor.
* Change: In Unicorn/cgt.py, when running a script, insert the current
working directory at head of the sys.path, not at the end. So installed
modules do not shadow local one.
* New: In Anabatic::Edge, new accessor "getRawcapacity()" to know the full
capacity of the edge, that is, the real maximum number of tracks that
can go through the associated side.
* Change: In Katana/BloatProfile/Slice::tagsOverloaded(), bloating policy
change, now bloat all the instances under the GCell, not only the first
one.
* Change: In KatanaEngine::runGlobalRouter(), restore the search halo growth
policy to expanding of 3 GCells every 3 iterations.
New metrics displayed, the edge wire length length overload.
* Change: In cumulus/plugins/ConductorPlugin.py, now accepts the following
configuration parameters:
- "anabatic.globalIterationsEstimate", maximum number of global
iterations during the bloating computation passes.
- "conductor.useFixedAbHeight", tells wether the additionnal blank
space must be added so the aspect ratio is kept or the height is
kept (and the block become wider).
Disable the display of "rubber" to unclutter a little the view.
* Bug: In Katana::BloatProfile::FlatInstance for X & Y calculation of
flattened instances reserse the order of transformation. We must apply
the occurrence path transformation to the instance transformation,
and not the other way around.
Was causing the bug in SNX example.
* Bug: In Katana::BloatProfile::Slice::tagOverloadeds(), the underlying
Gcell was not kept in synch with the instance. This was causing a right
shift of the bloated area.
* New: In Katana::BloatProfile, add the selection of overloaded edges and
failed nets.
Add a flag to KatanaEngine::runGlobalrouter() to choose what failed/
overloaded components to display (selectors).
This commit contains two set of features that should have been commited
separately.
1. Compliance with clang 5.0.1, tested with the RedHat collection
llvm-toolset-7. This allow Coriolis to be compiled under Darwin (MacOS)
with Xcode & macports. The bootstrap install system has been modificated
accordingly.
2. The basic support for routing density driven placement. Related
features are:
* Bloat property. Each Occurrence of an Instance can be individually
bloated. This property not attached to any tool to allow the placer and
router to share it as wanted. Nevertheless, it is defined in Etesian.
* BloatProfile in Katana, add individual Bloat properties to Instances
occurrences based on the East & North overflowed edges of each GCell.
* Support in ToolEngine for a "pass number" of a tool. This pass number
is mainly used to make "per pass" measurements. The MeasureSet system
is improved accordingly to support multiple values of a same measure.
* Embryo of "P&R Conductor" to perform the place & route loop until the
design is successfully placed. May be the first brick of a Silicon
Compiler.
* Change: In boostrap/FindBoostrap.cmake, in setup_boost(), added tag to
the python component for macport (ex: python27).
* Change: In boostrap/build.conf, put etesian before anabatic for
instance occurrence BloatProperty dependency.
Added option support for the "llvm-toolset-7" collection to build
against clang 5.0.1.
* Bug: In Hurricane::getRecord( const pair<T,U>& ), the getSlot<> templates
for first & second arguments must be called with <const T> and <const U>
as the pair itself is const (and not simply <T> & <U>).
* Change: In Hurricane::getSlot() temlate, only use "string" arguments and
not const string&, simpler for template argument deduction.
* Bug: In Hurricane::AnalogCellExtension, the StandardPrivateProperty<>
template has a static member "_name". Clang did show that the template
for this static number has to be put inside the namespace where the
template *is defined* (i.e. Hurricane) instead of the namespace where
it is instanciated (i.e. Analog).
* Bug: In Isobar, Matrix_FromListOfList(), PyInt_AsPlacementStatus() must
be put outside the C linkage back in the Isobar C++ namespace (clang).
* Bug: In Hurricane::DBo::~DBo, and derived add a throw() specification
(clang).
* Bug: In Hurricane::RegularLayer::getEnclosure() & setEnclosure(), change
signature so it matches the one of the base class (clang).
* Bug: In Hurricane::CellPrinter, use double brackets for initializer list
(clang).
* Change: In Hurricane::Breakpoint, reverse the meaning of the error level.
Only error level *lesser or equal* than the stop level will be enabled.
* Bug: In CRL/python/helpers/__init__.loadUserSettings(), must put the
current working directory in the sys.path as in certain configuration
it may not be included.
* Bug: In CRL::ApDriver, DumpSegments(), no longer generate segments when
encountering a RoutingPad on a top-level Pin Occurrence. The segment
was generated in the wrong direction, creating DRC violations on the
"mips_core_flat" example.
* Change: In CRL::Measures, partial re-design of the measurements management.
Now, each kind of measure can accept multiple values put in a vector.
The index is intented to match a tool run number.
* Change: In CRL::Histogram, add support for multiple sets of datas,
indexeds with tool run number.
* Change: In CRL::ToolEngine, add support for multiple pass number, add
addMeasure<> templates for the various data-types.
* Change: In CRL::gdsDriver & CRL::gdsParser(), comment out unused GDS record
name constants.
* New: Etesian::BloatProperty, property to attach to Instance occurrences
that contains the extra number of pitch to add to the cell width.
* Bug: In AutoSegment::CompareByDepthLength, the segment length comparison
was wrong, it was always returning true, which broke the "strick weak
ordering" of the comparison.
This was producing a core-dump in GCell::updateDensity() when sorting
a vector<>. The end() iterator was being dereferenced, leading to the
problem.
* Bug: In Katana::DataSymmetric::checkPairing(), the test for segments
whose axis is perpandicular to the symmetry axis was wrong
("!=" instead of "-").
* New: In Katana/GlobalRoute, new ::selectSegments(), selectOverloadedgcells()
and selectBloatedInstances() to automatically select segments from
overloaded edges, overloaded GCells and bloated cells.
* Change: In KatanaEngine, return a more detailed success state, distinguish
between global and detailed.
Add support for multiple routing iterations.
* New: In cumulus/python/plugins/ConductorPlugin.py, embryo of routing
driven placement.
* In CRL::Cyclop/CMakeLists.txt, add *again* the MOC files to the list
of .cpp . Don't know what is happening here with MOC under Qt 5.
* In CRL/python/helpers.io, cleanly fails if neither PyQt 4 nor PyQt 5 is
found. And tell it directly because this the module tasked to handle
the exceptions/errors...
* In Cumulus/plugins/AboutWindow.py, try PyQt 4 then PyQt 5.
* In documentation/UsersGuide, now tells explicitely that Qt 4 must be
used under RedHat 7 and Qt 5 under Debian.
* New: In bootstrap/coriolisEnv.py, add the "etc" directory to the
PYTHONPATH as initialization are now Python modules.
* New: In Hurricane/analogic, first groundwork for the integration of
PIP/MIM/MOM multi-capacitors. Add C++ and Python interface for the
allocation matrix and the list of capacities values.
* Change: In Hurricane::RegularLayer, add a layer parameter to the
constructor so the association between the RegularLayer and it's
BasicLayer can readily be done.
* Change: In Hurricane::Layer, add a new getCut() accessor to get the
cut layer in ViaLayer.
* Change: In Hurricane::DataBase::get(), the Python wrapper should no
longer consider an error if the data-base has not been created yet.
Just return None.
* Bug: In Isobar::PyLayer::getEnclosure() wrapper, if the overall
enclosure is requested, pass the right parameter to the C++ function.
* Change: In AllianceFramework, make public _bindLibraries() and export
it to the Python interface.
* Change: In AllianceFramework::create(), do not longer call bindLibraries().
This now must be done explicitely and afterwards.
* Change: In AllianceFramework::createLibrary() and
Environement::addSYSTEM_LIBRARY(), minor bug corrections that I don't
recall.
* Change: In SearchPath::prepend(), set the selected index to zero and
return it.
* Change: In CRL::System CTOR, add "etc" to the PYTHONPATH as the
configuration files are now organized as Python modules.
* New: In PyCRL, export the CRL::System singleton, it's creation is no
longer triggered by the one of AllianceFramework.
* New: In CRL/etc/, convert most of the configuration files into the
Python module format. For now, keep the old ".conf", but that are no
longer used.
For the real technologies, we cannot keep the directory name as
"180" or "45" as it not allowed by Python syntax, so we create "node180"
or "node45" instead.
Most of the helpers and coriolisInit.py are no longer used now.
To be removed in future commits after being sure that everything
works...
* Bug: In AutoSegment::makeDogleg(AutoContact*), the layer of the contacts
where badly computed when one end of the original segment was attached
to a non-preferred direction segment (mostly on terminal contacts).
Now use the new AutoContact::updateLayer() method.
* Bug: In Dijkstra::load(), limit symetric search area only if the net
is a symmetric one !
* Change: In Katana/python/katanaInit.py, comply with the new initialisation
scheme.
* Change: In Unicorn/cgt.py, comply to the new inititalization scheme.
* Change: In cumulus various Python scripts remove the call to
helpers.staticInitialization() as they are not needed now (we run in
only *one* interpreter, so we correctly share all init).
In plugins/__init__.py, read the new NDA directory variable.
* Bug: In cumulus/plugins/Chip.doCoronafloorplan(), self.railsNb was not
correctly managed when there was no clock.
* Change: In cumulus/plugins/Configuration.coronaContactArray(), compute
the viaPitch from the technology instead of the hard-coded 4.0 lambdas.
In Configuration.loadConfiguration(), read the "ioring.py" from
the new user's settings module.
* Bug: In stratus.dpgen_ADSB2F, gives coordinates translated into DbU to
the XY functions.
In st_model.Save(), use the VstUseConcat flag to get correct VST files.
In st_net.hur_net(), when a net is POWER/GROUND or CLOCK also make it
global.
* Change: In Oroshi/python/WIP_Transistor.py, encapsulate the generator
inside a try/except block to get prettier error (and stop at the first).
* Bug: In Katana::SegmentFsm CTOR, when computing costs for METAL2 in
non-preferred direction attached to METAL1 terminals, do not try to
align on a METAL3 track, as there may be not. Especially when the
METAL3 pitch is not multiple of the METAL1 one.
Compute at least one cost (with the same axis as the vertical METAL1
terminal).
* Change: In Etesian::BloatCells, adjust the "90%" bloat profile for a
METAL3 pitch of 8 lambdas (sligh decrease).
* Bug: In cumulus/plugins/ChipPLace.py, import chip.Chip, not only chip.
* Change: In Hurricane::Script, when running a script, no longer do it
inside a Python sun-interpreter, use the current one. This way we
no longer have our modules initialized twice or more, which was
starting to be unmanageable (with the NDA support).
The settings were re-read multiple time to the same value, so it
was working, but still...
I hope I didn't left some dangling Python objects now.
* Bug: In Hurricane::LayoutGenerator::drawLayout(), get the device abutment
box though a Pyhon object *before* finalizing which removes that objet.
* New: In cumulus/plugins/__init__.py, add a "loadPlugins()" and static
initialisation to preload plugins modules.
We use that pre-loading step to append to the module __path__ attribute
the alternate directory where a NDA covered may be found. This assume that
the directory tree under the NDA root is identical to the one under the
public root.
* New: In cumulus/plugins/chip/__init__.py, small utility function
importContants() to import the constants inside another module namespace,
to have more consise notations.
* Change: In cumulus/plugins/, in the various plugins sub-modules import
use the full path from plugins, that is, for example:
from plugins.core2chip.CoreToChip import IoPad
* Change: In Unicorn/python/unicornInit.py, no longer directly load the
plugins modules, this is now done by cumulus/plugins/__init__.py.
Instead, iterate through sys.modules for the ones starting by "plugins/"
and try to execute a Unicorn hook, if present.
* Change: In Karakaze/python/AnalogDesign.py, update for the new Instance.create()
prototype (added placement parameter).
* New: In CRL::ApDriver::DumpSegments(), drive as top-level segments the
RoutingPads using a Pin, and not only using a segment. They are not
exported as top level Pin but only as Segment as they do belong to
a deeper level.
* New: In Cumulus/plugins/PadsCorona.Side._placePads(), now manage both
"pxlib" and "phlib*". Pad library management is still hardcoded, this
should be made a configuration option someday.
* Change: In Anabatic::GCell::updateDensity(), all non-passthrough wires
now have a cost of 0.5 instead of 0.33 for locals.
* Change: In Manipulator::canMoveUp(), increase the "reserve" amount to
1.0 for "far from terminal" wires (rpDistance > 2).
* Change: In NegociateWindow::NegociateOverlapCost(), always sets "AtRipupLimit"
when the overlapping segment is nearing it's maximum ripup limit.
(different detection for non-preferred and regular)
* Change: In SegmentFsm::_slackenStrap(), call avoidBlockage() if it is
overlapping a blockage *or* a segment at it's ripup limit. I hope I
didn't create an infinite loop here.
* Bug: In cumulus/plugins/PadsCorona.py, CoreWire._computeCoreLayers(),
the big contact between symbolic and real was badly computed for
east/west (was using width instead of height, bummer!).
In Corona._createCoreWire(), completly screwed computation of the
side gap, was using a badly initialized value of the "bb" variable.
* Bug: In cumulus/plugins/Chip.py, the computation of the minimal size
for the corona was wrong, do *not* add the size of the pads and
multiply by two as it is done by "inflate". This was forcing the user
to create way to large chips for a given core size.
This commit degrades the run success rate of ARMv2a to 87% (40 iters).
* New: In CRLcore/etc/.../kite.conf, add configuration parameters:
katana.termSatReservedlocal
katana.termSatthreshold
for the new edge capacity computation system.
* New: In CRLcore/etc/symbolic/phenitec06/, add support for N. Shimizu
small I/O pads (supplied in phlib80). Tune various parameters of
Anabatic/Katana to increase routing success.
* Change: In CRLcore/alliance/ap/ApParser, make Pin external components,
so RoutingPad will be build upon in global routing.
Do not complain when a I/O pad has a physical instance that did
not exists in the netlist. Just create it (appeared in phlib80).
When no netlist instance exists in a pad, the pad Cell is still
considered as terminal.
* New: In Etesian::BloatCells, new profile named "3metals" better suited
for two routing metals technologies (i.e. Phenitec).
* New: In Anabatic::RawGCellsUnder, new CTOR which take only source &
target points instead of a segment. Needed to manage wide segment for
which the axis to consider is not that of the segment (one axis for
each track it intersect).
* New: In Anabatic::GCell, add a RoutingPad count attribute, for Edge
reservation computation.
* New: In AnabaticEngine::computeEdgeCapacities(), instead of decreasing
all edges of a fixed amount (hTrackReservedLocal), guess the GCell
cluttering from the number of RoutingPads that it contains.
For non-saturated GCells, the four edges are decreased by the number
of RoutingPads. We use the maximum from the two neigboring GCells.
The hTrackReservedLocal parameter is now used only as a *maximum*
that the edge reservation can reach.
If a GCell is saturated (more than 8 RoutingPads, the saturation is
propagated horizontally to 2 neigboring GCells).
* Change: In AutoContactTerminal::getNativeConstraintBox(), use a more
flexible gauge name matching for terminal vertical extensions correction.
Namely, match all "msxlib*" kind of gauges.
* Change: In AutoSegment::setAxis(), add the ability to force the axis
position, even if it is a non-canonical segment. Maybe needed in the
initialisation steo, before the first canonisation is performed.
* New: In NetBuilder, added new methods _do_1G_1PinM1() and _do_2G_1PinM1(),
to manage coronas for Phenitec designs.
To avoid various side effects from segments being too close from
the north / east side of the routing area, make those segments fixeds.
* Change: In KatanaEngine::annotateGlobalGraph(), the management of wide
wires was wrong. The axis to use to find the underlying GCells is the
one of the track, not of the segment. This was creating bad edge
capacity computation under the power ring of a block and subsequently
routing failures.
* New: In Kanata::Manipulator, added method reprocessParallels(), not used
though, but keep it anyway, might be of use later...
* New: In Kanata::Manipulator, added method avoidBlockage() for terminal
METAL2 in non-preferred direction, restrict the terminal and turn
constraint box at the current position of the perpandicular, so it
doesn't create a deadlock in METAL2.
* Change: In SegmentFsm::conflictSolveByPlaceds(), if we cannot break
using the whole overlap, try the first atomic overlap.
* New: In SegmentFsm::_slackenStrap(), manage conflict between a non-prefered
segment and a blockage, this when to call avoidBlockage()...
* New: In Katana::Configuration, management of the new edge computation
parameters:
katana.termSatReservedlocal
katana.termSatthreshold
* New: In Cumulus/plugins/Core2Chip, support for Phenitec I/O pads.
* Bug: In cumulus/plugins/PadsCorona.py, when a pad is at the beginning
or at the end of the side, the pad corona terminal may be outside
the corona range (not directly facing it). In that case, create a
bend to reach it.
Worse, in some case more than one (but likely no more), could be
in that case, so not only do we create a bend but also make a
shift in the bended segment so two consecutive ones are not on the
same axis, causing shorts.
If both end pads of a corner are in that case, we cannot prevent
a short, so at least, issue a warning.
* Bug: In CRL::Vhdl, the Entity::VstUseConcat was not passed correctly
along, so we did get a strange mix of conat and direct assignment.
* New: In Unicorn/cgt.py : added --vst-use-concat options to control
the VST driver behavior.
* New: In CRL/etc/symbolic/phenitec06, configuration for symbolic
layout targeted for Phenitec 0.6um (do not contains any NDA
covered informations). Could be used for any 3 metal layers
techno.
* Bug: In Cumulus/plugins/chip/Configuaration.py, _setStackposition()
disable stack error when there is no slave component on the stack
(happens when the stack consists only of one contact).
* Change: In Cumulus/plugins/chip/PadsCorona, if the external pins of
the corona are in GCells that are also under the core block ring
power lines, they are flagged as "go straight" and this produce
impossible configurations for the router to solve. Now we ensure
that there is one free GCell all around the corona border.
* Bug: In Cumulus/plugins/chip/Configuration.py & PadsCorona.py,
at the begin/end of a side of pad, connectors can be outside the
corona range (i.e. not directly face to face). Now make a dogleg
if needed. This is a work in progress as if there are two of them,
they will short on the perpandicular part. We must compute a
shift.
* Bug: In Cumulus/plugins/core2chip/CoreToChip.py, when creating the ioNet
objects, when a signal is an enable we must not set the external chip
net (the name for the PAD terminal) as it may be set later if it is
also used as an individual pad.
* Change: In Cumulus/plugins/core2chip/CoreToChip.py, in IoNet select
the external I/O net (pad connected) signal to be generated in the
context of the I/O pad instanciation. This should allow an enable
signal in one pad to be also used in a direct output pad.
* New: In Cumulus/plugins/CoreToChip, added support for Tristate ouput
pads and bidirectional pads.
Added capability to name the I/O pad instance and their external
terminals so we can override the default naming scheme.
Mandatory anyway for bidirectional and tristate I/O pad as we
cannot guess the core net grouping (in/out/enable).
Support is available for symbolic CMOS and AMS c35b4 (but not
published due to NDA).
* Change: In Cumulus/plugins/chip/Configuration.py, the configuration
file is now named simply "ioring.py" instead of being prefixed by
the design name. As a consequence we can have only one chip per
directory. But now all the tools, for any design in that directory
can peek datas into it.
* Change: In Hurricane::Cell_LeafInstanceOccurrences, add the ability to
walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell_NonLeafInstanceOccurrences, add the ability to
walkthrough the leaf of one specific top-level instance.
* Change: In Hurricane::Cell:
getLeafInstanceOccurrences() and getNonLeafInstanceOccurrences(), now
have a parameter Instance* to select the leafs we want to walk through.
If set NULL (default value) browse through all the instances,
as before.
* Change: In Hurricane::DeepNet, add forgotten Inspector support.
* New: In EtesianEngine, add a "block" (and Instance) attribute to allow
the placement of one specific bloc. If we want to place the core of
a chip and take into account the external terminals (if they are not
already fixed as Pins at the edge of *said* block). We must place
the core *in the context* of it's instanciation in the corona.
Note for G. Gouvine : Pin & external RP should be taken into account
starting at line 629 of EtesianEngine.cpp...
* New: In cumulus/plugins/chip/Chip.py, make use of the new block
placement feature of ETesian.
* Bug: In KatanaEngine::create(), perform a pre-check to prevent trying to
route whole chip, which is forbidden an leads to annoying core-dumps.
Routing must take place "at most" at Corona level.
* Bug: In KatanaEngine::PowerRails, create a plane for METAL1 blockage.
Not completely sure this was a bug...
* Change: In Hurricane::SharedName, replace the incremental Id by a hash key.
This is to ensure better deterministic properties. Between use cases,
additional strings may have to be allocated, shitfing the ids. Even if
hash can be duplicated, we should be able to ensure that the absolute
order in map table should be preserved. Supplemental strings are inserted
in a way that keep the previous order.
* Change: In CRL/etc/symbolic/cmos/kite.conf, add "katabatic.routingGauge"
default parameter value ("sxlib").
* Change: In CRL/etc/common/technology.conf, define minimal spacing for
symbolic layers too (added for METAL4 only for now).
* Change: In CRL::Histogram, extend support to dynamically sized histograms.
Add a text pretty print with table and pseudo-curve.
* Change: In Cumulus/plugins/ClockTreePlugin, create blockage under the
block corona corners so the global router do not draw wire under them.
This was creating deadlock for the detailed router.
When the abutment has to be computed, directly use Etesian to do it
instead of duplicating the computation in the Python plugin.
* New: In Etesian, as Coloquinte seems reluctant to evenly spread the
standard cells, we trick it by making them bigger during the placement
stage. Furthermore, we do not not uniformely increase the size of the
cells but create a "bloating profile" based on cell size, cell name
or it's density of terminals. Currently only two profiles are defined,
"disabled" which does nothing and "nsxlib" targeted on 4 metal layer
technologies (aka AMS 350nm, c35b4).
* Bug: In Knik::MatrixVertex, load the default routing gauge using the
configuration parameter "katabatic.routingGauge" as the default one
may not be the first registered one.
* New: In AnabaticEngine::setupNetDatas(), build a dynamic historgram of
the nets terminal numbers.
* Bug: In Anabatic::AutoContact::Invalidate(), always invalidate the
contact cache when topology is invalidated. In case of multiple
invalidations, if the first did not invalidate the cache, later one
that may need it where not allowed to do so. The end result was correct
nonetheless, but it did generate annoying error messages.
* Bug: In Anabatic::AutoContactTurn::updateTopology(), bad computation
of the contact's depth when delta == 2.
* Bug: In Anabatic::Gcell::getCapacity(), was always returning the west
edge capacity, even for the westermost GCell, should be the east
edge in that case.
* New: In Anabatic::AutoSegment, introduce a new measure "distance to
terminal". This is the minimal number of segments separating the
current one from the nearest RoutingPad. This replace the previous
"strong terminal" and "weak terminal" flags.
This distance is used by Katana to sort the events, we route the
segments *from* the RoutingPads *outward*. The idea being that if we
cannot event connect to the RoutingPad, there is no points continuing
as thoses segments are the more constraineds. This gives an order close
to the simple ascending metals but with better results.
* New: In Anabatic::AutoSegment, introduce a new flag "Unbreakable", disable
dogleg making on those segments. mainly intended for local segments
directly connecteds to RoutingPads (distance == 0).
* New: In Anabatic::AutoSegment, more aggressive reducing of segments.
Now the only case where a segment cannot be reduced is when it is
one horizontal branch in a HTee or a vertical on a VTee. Check if,
when not accounted the source & target VIAs are still connex, if so,
allow reducing.
* New: In Anabatic::AutoContact, new state flags CntVDogleg & CntHDogleg
mainly to prevent making doglegs twice on a turn contact. This is to
limit over-fragmentation. If one dogleg doesn't solve the problem,
making a second one will make things worse only...
* Bug: In Anabatic::Configuration::selectRpcomponent(), we were choosing
the component with the *smallest* span instead of the *bigger* one.
* New: In Anabatic::GCell, introduce a new flag "GoStraight" to tell that
no turn go be made inside those GCells. Mainly used underneath a block
corona.
* New: In AnabaticEngine::layerAssign(), new GCellRps & RpsInRow to manage
GCells with too many terminals. Slacken at least one RoutingPad access
when there is more than 8 RoutingPad in the GCell (slacken or change
a vertical METAL2 (non-preferred) into a METAL3).
* Change: In Anabatic::NetBuilderHV, allow the use of terminal connection
in non-preferred direction. That is, vertical METAL2 directly connected
to the RoutingPad (then a horizontal METAL2). This alllows for short
dogleg without clutering the METAL3 layer (critical for AMS c35b4).
Done in NetBuilderHV::doRp_Access(), with a new UseNonPref flag.
Perform some other tweaking on METAL1 access topologies, to also
minimize METAL3 use.
* New: In AnabaticEngine::computeNetConstraints(), also compute the
distance to RoutingPad for segments. Set the Unbreakable flag, based
on the distance and segment length (local, short global or long global).
New local function "propagateDistanceFromRp()".
* Change: In AnabaticEngine.h, the sorting class for NetData, SparsityOrder,
is modificated so net with a degree superior to 10 are sorted first,
whatever their sparsity. This is to work in tandem with GlobalRouting.
* New: In Katana::TrackSegmentNonPref, introduce a class to manage segment
in non-preferred routing direction. Mostly intended for small METAL2
vertical directly connected to RoutingPad. Modifications to manage
this new variant all through Katana.
* Change: In Katana::GlobalRoute, DigitalDistance honor the GoStraight flag
of the GCell. Do not make bend inside thoses GCells.
* Change: In KatanaEngine::runGlobalRouter(), high degree nets (>= 10) are
routed first and whitout the global routing estimation. There should be
few of them so they wont create saturations and we want them as straight
as possible. Detour are for long be-points.
Set the saerch halo to one GCell in the initial routing stage (before
ripup).
* Bug: In KatanaEngine & NegociateWindow, call _computeCagedconstraints()
inside NegociateWindow::run(), as segments are inserted into tracks
only at that point so we cannot make the computation earlier.
* Change: In Katana::Manipulator::repackPerpandiculars(), add a flag to
select whether to replace the perpandiculars *after* or *before* the
current segment.
* Change: In Katana::NegociateWindow::NegociateOverlapCost(), when the
segment is fully enclosed inside a global, the longest overlap cost
is set to the shortest global hoverhang (before or after).
When the cost is for a global, set an infinite cost if the overlapping
segment has a RP distance less or equal to 1 (this is an access segment).
* Bug: In Katana::PowerRailsPlane::Rail::doLayout(), correct computation of
the segments extension cap.
* New: In Katana::QueryPowerRails::addToPowerRail(), add support for Pad.
* Change: In Katana/PreProcess::protectCagedTerminals(), apply the contraints
to any turn connected to the first segment of the RoutingPad so the
perpandicular constraints got propagated to the perpandicular segment...
* Change: In RoutingEvent, cache the "distance to RP" value.
* Change: In RoutingEvent::Key::compare(), sort *first* on distance to
RoutingPad, then layer depth. If both distance to RoutingPad is null,
then sort on segment length.
* Change: In RoutingEvent::_processRepair(), try a repack perpandicular with
perpandiculars first (then with perpandicular last, then give up).
* Change: In SegmentFsm::bindToTrack() and moveToTrack(), set an axis hint
when creating the insertion event.
* Change: In SegmentFsm::_slackenStrap(), add a step through slacken between
minimize and maximum slack (wihch directly end up in unimplemented).
* Change: In Session::_addInsertEvent(), add an axis parameter needed when
the axis of the segment is not the one of the track (case of wide
segments or non-preferred direction).
* Bug: In Track::_preDestroy(), bad management of the TrackElement reference
count. Destroy the segment only when reaching zero...
* Bug: In Track::expandFreeIneterval(), forgotten to manage case when there
is a set of overlaping segments at the "end" of the track, the
EndIsTrackMax was not set.
* Change: In TrackCost::Compare, increase the cost when an overlaping
segment is at it's ripup limit. We should try *not* to rip it up if
we can. Add a dedicated flag "AtRipupLimit".
* Change: In TrackElement, add proxies for isUnbreakable(), new function
updateTrackSpan().
* New: In TrackFixedSegment CTOR, when a supply wire of METAL2 or above is
found, make the underlying GCells "GoStraight".
* New: In TrackElement::canDogleg(GCell*), check for already done perpandicular
dogleg on source/target (reject if so).
* New: In Isobar::PyCell, export the isRouted() and setRouted() to the
Python interface.
* Bug: In CRL::Entity::parseEntity(), check that the closing parenthesis
is the last character of the net name. Issue a more relevant error
message.
* In Anabatic::NetBuilder::_do_xG() and all other unimplemented methods,
throw an error if called from a derived classes instead of just
issuing a message in the debug stream. Avoid later core dumps...
* In Anabatic::NetBuilderHV, implement the builders for GCells with
one pin. Needed to support chip/corona routing.
* Bug: In Cumulus/plugins/Chip.py, check that coronaCk exists before
using it.
* New: In Cumulus/plugins/PadsCorona/Side._placePad(), when routing
a design with symbolic pads, export the chip external "pad"
connectors to be able to perform a lvx (otherwise cougar do not
create external nets).
In Corona._createCoreWire(), set the minimal gap between the pads
and the corona to 6 pitches. Empirical value to avoid DRC errors
with symbolic pads (pxlib).
When successufully done, mark the Corona cell as routed.
* Bug: In Cumulus/plugins/Core2Chip.IoNet, the regex for vectorizet net
was wrong, it was allowing only one digit in the index.
* Bug: In Cumulus/plugins/Core2Chip.cmos, correct management of
pad & corona clock nets. Correct connexion between vdde/vddi.
* Bug: In Unicorn/cgt.py, forgot to execute scripts when in text mode.
* Change: In Hurricane::Error constructors disable the backtrace generation.
(*very* slow).
* Change: In Hurricane::Library::getHierarchicalname(), more compact
naming. Remove the name of the root library.
* New: In Hurricane::Net, new type "FUSED", for component with no net.
More efficient than having one net for each.
* Change: In CellViewer, BreakpointWidget, use Angry Birds icons.
* Change: In CellWidget::State, use the hierarchical name (cached) as key
to the state. This allow to load two cells with the same name but from
different libraries in the widget history.
* Change: In PyGraphics, export "isEnabled()" and "isHighDpi()" functions.
* Change: In CRL/etc/symbolic/cmos/plugin.conf, and
CRL/etc/common/plugin.conf use the physical dimensions converters.
* Change: In CRL/etc/symbolic/cmos/technology.conf, make the GDS layer
table coherent with the default Alliance cmos.rds.
* New: CRL/python/helpers/io.py, put ErrorMessage new implementation here,
along with a new ErrorWidget written in PyQt4. It seems finally that
PyQt4 can be used alongside Coriolis Qt widgets.
New ErrorMessage.catch() static function to manage all exceptions
in except clauses.
* Change: In CRL/python/helpers/, no longer use ErrorMessage.wrapPrint(),
directly print it.
Rewrite the utilities to display Python stack traces "textStacktrace()"
and "showStacktrace()".
* Change: In CRL::AllianceFramework, shorten the names of the libraries.
* Change: In CRL::ApParser & CRL::ApDriver, more accurate translation between
Alliance connectors (C record) and Hurricane::Pin objects. Pin are no
longer made square but thin and oriented in the connecting direction.
Use the new fused net for unnamed components.
* New: In CRL::GdsParser, implementation of SREF parsing, i.e. instances.
Due to the unordered nature of the GDS stream, instances creation are
delayed until the whole stream has been parsed and only then are they
created.
For the sake of reading back Alliance s2r GDS, we assume that any
TEXT following a boundary is the Net name the boundary (component)
belongs to.
Create abutment box for Cells, computed from the bounding box, so
the Hurricane QuadTree could work properly.
Make use of the fused net for unnamed components.
* New: In Cumulus/plugins/chip, complete rewrite of the I/O pad management.
Now we can mix real (foundry) pads and a symbolic core.
To cleanly support the de-coupling between the real part and the
symbolic one we introduce a new intermediary hierarchical level, the
corona. We have now:
Chip --> Pads + Corona --> Core.
At chip level (and if we are using real pads) the layout is fully
real (excepting the corona).
The Corona contains everything that is symbolic. It has symbolic
wires extending outward the abutment box to make contact with the
real wires coming from the pads.
In the pad ring we can use corners instances (or not), pad spacers
or directly draw wires between connectors ring pads.
Provide two flavors: placement only or full place & route.
WARNING: If routing in a second step, *do not route* the *Chip* but
the *Corona*.
* Change: In Cumulus/plugins/clocktree, give the modified Cell an
additional extension of "_cts" (Clock Tree Synthesis) instead of
"_clocked", to follow the common convention.
* New: In cumulus/plugins/S2R.py, encapsulate call to Alliance S2R and
reload the translated Cell in the editor.
* New: In cumulus/plugins/core2chip, provide an utility to automatically
create a chip from a core. To work this plugins must have a basic
understanding of the pad functionalities which may differs from
foundry to foundry. So a base class CoreToChip is created, then for
each supported pad foundry a derived class is added. Currently we
support AMS c35b4 and Alliance symbolic cmos.
* Bug: In Anabatic::Configuration, read the right configuration parameter
"anabatic.topRoutinglayer" (Katana), and not the one for Katabatic...
* Change: In Unicorn/cgt.py, process the plugins in alphabetical order
to ensure a reproductible ordering of the menus...
* Bug: In CRL/etc/symbolic/cmos/plugins.conf, rails dimensions are no
longer expressed directly in lambda. Must be created using helper.l().
* Change: In CRL::ApParser, slightly more smart management of Pin width.
Must normalize Pin behavior between Alliance & Hurricane as in
Alliance they have only one dimension.
* Change: In CRL::LefImport, if a net name end with "!", assume it's a
global one. Have to check this naming convention.
* Change: In Anabatic::NetBuilderHV::_do_1G_1PinM3() & _do_1G_1PinM2()
now implemented. Needed for the corona routing support.
* Change: In AnabaticEngine::setupPreRouted(), exclude segments outside
the abutment box.
* Change: In KatanaEngine::PowerRails, remove the I/O pad support as now
we route only inside the Corona. So only one vdd/vss/ck are supported.
* New: In cumulus/plugins/ChipPlugin.py, complete rewrite of the chip
support:
* Uncouple pad I/O ring whith real cells (foundry) from a symbolic
core. A new intermediate level "corona" is introduced to handle
the real/symbolic transition.
* Ability to explicitly setup position of the pads on the chip side
in case of uneven distribution.
* Enable clock tree to be build with 3 metal only (M2 to M4) instead
of (M2 to M5).
* Bug: In Hurricane::Cell::flattenNets(): Same error again, do not create
components while iterating over the components Collection.
Now RoutingPad of top nets are create outside the loop as they must.
* New: In Hurricane::Isobar::PySegment, added wrapper for getOppositeAnchor().
* Bug: CRL::PyRoutingLayerGauge, Python wrapper of getTrackPosition() was
in fact returning getTrackNumer().
* Bug: In Katana::PowerRailsPlanes::Rail::doLayout(), add the half minimum
distance to the blockage segments extensions. Was causing too near
VIAs is cmos45.
* Change: In cumulus/plugins/ClockTree, correctly manage routing gauge when
the lower pitches (M2/M3) is different from the upper one (M4/M5).
But we still can only do sxlib compliant gauges because we do not
handle a switch in preferred routing directions.
* New: In Katana::TrackCost, the TrackElement and it's optional
symmetric are now kept as attribute of a TrackCost. The cost
is completly computed inside the constructor.
TrackCost now support any mix of symmetric event and wide
segments.
The cost is now computed by adding directly to the current
one instead of creating secondaries that are merged afterwards.
As a consequence, remove all copy construction and merge
capabilities.
All the various methods used to compute the cost are renamed
"addOverlapcost()" in all the various related objects.
As a reminder, the overal cost method call is as follow:
1. TrackCost constructor on a TrackElement.
2. Call TrackElement::addOverlapcost()
3. For all Track under the TrackElement, call
Track::addOverlapCost()
4. For all other TrackElement intersecting with
the overlap interval call:
TrackElement::incOverlapCost()
5. The callback overlap function for segments
is called (defined in NegociateWidow).
Don't confuse:
- TrackElement::addOverlapCost(), which compute the cost of
inserting the segment inside a track (or a set of).
- TrackElement::incOverlapCost(), which compute the cost of
overlaping with this already inserted segment. It is the
other way around of the previous one.
* Change: In Katana::SegmentFsm, use a vector of pointer to TrackCost
instead of an object to avoid copy construction.
* Change: In all top CMakeLists.txt, force the use of Python 2.7 as
we do not compile against 3.x flavors. Do not use the "EXACT"
flags as it will not recognize 2.7.x versions.
* Change: In Katana::RoutingEvent::Key::Compare(), preliminary
experiments shows that the best sorting order is:
- Lower layer first (i.e. M2 -> M3 -> M4 -> ... )
- Longer segments first.
The later seems to be counter-intuitive. Guess is that placing
the small ones first generate a more important fragmentation of
the big ones. They are placed too early and are difficult to move
afterwards.
Another feature to test is *not* inserting pushed left/right
segments if they are not *already* routed.
* Change: In PyKatanaEngine.runNegociate() now takes a flag argument,
provided through the new PyKatanaFlags exported object.
(doChip.py must be changed accordingly)
* Bug: In Hurricane::Net::setExternal(), do not perform an UpdateSession
inside this function, it leads to unbearibly slow operation in the
clock-tree plugin.
* Bug: In Kite, backport corrections done in Katana and also relevant
for Kite.
* New: In Cumulus.ChipPlugin.py add support for Python profiling with
cProfile. Disabled under normal operation, but will certainly come in
handy sometimes.
* Bug: In Cumulus & Stratus, now that creation of Hurricane objects must be
enclosed in UpdateSession, has to adds them into Python code.
* Bug: In Anabatic & Katana, in the global routing stage suspend the timed
bewteen ripup steps instead of resetting it.
* Bug: In Cumulus, in ClockTree plugin in GaugeConf._rpAccess() do not
create the stack of access VIAs each time the function is called.
Instead maintain a lookup table of the already generated ones.
Was blocking the loading of pre-routed nets in Anabatic.
* Change: In Stratus, in dpgen_RAM, the cell height was fixed to 50l.
Now read the prech[0] to set up the cell height (useful for MOSIS
cells).
* New: In Stratus, in buildModel(), the stand alone generator caller
now support a className, a modelName and a set of parameters to
pass on to the model. This is very useful when the module name
(the file), the class name and the model name are not the same.
* In Hurricane, in Cell::flattenedNets(), if the cell has already been
flattened, do not issue warnings about duplictated flattened nets.
* In Hurricane, in Net, allow Net::setName() to switch the main name
for an alias without complaining about an already used name.
* In Cumulus, in RSavePlugin.py, when "views" is supplied in keywords
(kw) arguments, override the default instead of merging with it.
This is to allow scripts to save exactly what views they want.
* Change: In Hurricane, in DataBase::CellDepths() the recursion stop
criterion must be Cell::isLeaf() and not Cell::isTerminal() as
the second one can be used to hide some levels of hierarchy,
and we want all of them in a blob.
* New: In Hurricane, in Cell, create a new Slaveds relation to keep
track of all the Cells with a slaved abutment box. This work is
incomplete as we do not manage the behavior in case of merge or
Cell destruction or slaving Cells with aready slaveds ones.
Modify Cell::setAbutmentBox() to work in both autonomous and
slaved mode.
* New: In Hurricane, in Net, add a new type of Net: BLOCKAGE this
avoid us to be dependant on the framework pattern recognition.
(change propagated to the Python support)
* New: In CRL Core, in the various drivers, recognize blockage nets
as such and set their type accordingly.
* Change: In CRL, in Toolbox::deleteEmptyNets(), preserve blockage
Nets. This was the cause of crashs in Kite::BuildPowerRails() as
we where trying to use a deleted blockage net...
* Bug: In Hurricane, in NetAlias, do not write NetAlias as a name
but as a type. They were not read back and moreover staying in
the JSON parser stack.
* Bug: In CRL Core, in BlifParser, recognize clocks (Alliance patterns).
* Change: In Cumulus, in RSavePlugin, "kw" manage a new "views" to
specify which views must be saved. Physical by default, but sometimes
we need logical as well. If the design contains uniquified cells,
save the logical view.
In ClockTree, abort the clock tree building if the design has no
top level clock.
* Change: In Katabatic, in GCellTopology, adds 2G_5M1 configuration.
* Bug: Kite, in BuildPowerRails, if we are not in a chip the nets
composing the H-Tree must be protecteds be blockages.
* Change: In Knik, in Vertex, add a "blocked" flag to signal disabled
vertexes in the grid (must not be used by the global router).
Modificate the Graph::getVertex() method so that when a vertex
is geometrically queried, if is a blocked one, return a non-blocked
neighbor. This mechanism is introduced to, at last, prevent the
global router to go *under* the pad in case of a commplete chip.
* New: In Katabatic, in AutoSegment, a new state has been added: "reduced".
A reduced segment is in the same layer as it's perpandiculars.
To be reduced, a segments has to be connected on source & target to
AutoContactTurn, both of the perpandiculars must be of the same layer
(below or above) and it's length must not exceed one pitch in the
perpandicular direction.
To reduce an AutoSegment, call ::reduce() and to revert the state,
call ::raise(). Two associated predicates are associated:
::canReduce() and ::mustRaise().
Note: No two adjacent segments can be reduced at the same time.
* Bug: In Katabatic, in GCellTopology, add a new method ::doRp_AccessPad()
to connect to the pads. Create wiring, fixed and non managed by
Katabatic, to connect the pad connector layer to the lowest routing
layers (depth 1 & 2). The former implementation was sometimes leading
to gaps (sheared contact) that *must not* occurs during the building
stage.
Remark: This bug did put under the light the fact that the initial
wiring must be created without gaps. Gaps are closed by making doglegs
on contacts. But this mechanism could only work when the database if
fully initialised (the cache is up to date). Otherwise various problems
arise, in the canonization process for example.
* New: In Katabatic, in AutoContactTerminal::getNativeConstraintBox(),
when anchored on a RoutingPad, now take account the potential rotation
of the Path's transformation. Here again, for the chip's pads.
* New: In Kite, support for reduced AutoSegment. TrackSegment associateds
to reduced AutoSegment are *not* inserted into track to become
effectively invisibles. When a segment becomes reduced, a TrackEvent
is generated to remove it. Conversely when it is raised a RoutingEvent
is created/rescheduled to insert it. All this is mostly managed inside
the Session::revalidate() method.
* New: In Kite, in KiteEngine::createGlobalGraph(), in case of a chip,
mark all global routing vertexes (Knik) that are under a pad, as blockeds.
* Bug: In Cumulus, in PadsCorona.Side.getAxis(), inversion between X and
Y coordinate of the chip size. Did not show until a non-square chip
was routed (i.e. our MIPS R3000).
* Change: In Stratus1, in st_placement.py add the ClockBuffer class for
backward compatibility with the MIPS32 bench. Have to review this
functionnality coming from the deprecated placeAndroute.py.
In st_instance.py, no longer creates the Plug ring of a Net.
In my opinion it just clutter the display until the P&R is called.
Can re-enable later as an option (in Unicorn).
* Change: In Unicorn, in cgt.py, more reliable way of loading then running
user supplied scripts. Borrowed from alliance-checker-toolkit doChip.py .
* New: In Hurricane, in Cell & Instance, add the ability to merge the
QuadTree when *second level* instances of a Cell are placed in
the same space as the top Cell. This is the case of a deeply
hierarchical design made of only standard cells that are to
be placed in a "flat" manner.
The design is uniquified then the intermediate instances models,
which should be unique at that point have their QuadTree merged
through a call to Instance::slaveAbutmentBox(). That method will
make the model of the instance use the QuadTree of the Cell to
which the instance belong. The instance model no longer posseses
a dedicated QuadTree. As a corollary the abutment box of both
Cell are kept identical and the Instance has it's transformation
set to (0,0,ID).
Remark: when we talk about "QuadTree", we mean in fact the
QuadTree for the instances *and* the SliceMap (Layer+QuadTree).
Consequence in Query: when going through the resulting
"flattened" QuadTree we will find objects with an incomplete
Path du to the fact that we didn't have to explore their
Instance/Cell level to reach them. The shunted part of the
Path is stored in the Go master Cell in the _shuntedPath
attribute. This also affect the displayed depth of hierarchy,
but not too badly.
* New: In Hurricane, in Cell, new methods:
- Cell::updatePlacedFlag() : set the placement flags.
- Cell::isUnique() : one or less instance.
- Cell::isUniquified() : is the result of an uniquification.
- Cell::isUniquifyMaster() : is the reference cell of the
uniquification.
* Change: In Hurricane, in Cell::Uniquify(), uniquify a Cell only
if it is unplaced. We do not need to duplicate placed Cells
(see datapathes).
* New: In Kite, in BuildPowerRails more accurate GCell density computation
under the pad area, to limit the overloaded messages.
* New: In Cumulus, In BlockCorona, remove the vertical METAL3 blockages
and replace them by horizontal blockages completly enclosing the
corona big vias in all layers. This way the I/O wires that goes
through the corona are guided to be straight and do not creates
unsolvable doglegs due to the presence of big vias.
* Change: In Kite & Etesian, small typo: refactor the method
"::wipeOutRouting()" into "::wipeoutRouting()" (indulge me, I'm a
code maniac).
* Bug: In Hurricane, in PyHurricane.h the macro HCATCH was not catching
standard STL exceptions. This was the source of the cryptic message:
"Fatal Python error: Py_EndInterpreter: thread still has a frame"
The Python interpreter was interrupted uncleanly bypassing it's own
exceptions mechanism.
In PyViewer, the Viewer *do not* inherit from a base class (in the
Python export).
* New: In Hurricane, in DbU, compute maximum values (in double) for
grid, lambda & physical (in meter) so now the DbU::toGrid(),
DbU::toLambda() & DbU::toPhysical() methods can check for out of
bound values, and throw an exception.
* Change: In Hurricane, ExceptionWidget::catchAllWrapper() now returns
a boolean, set to <true> if an exception has been catched. Allow
callers to interrupt themselves if a problem has occured.
* Bug: In Kite & Etesian, in the Python wrapper, send a Python exception
if catchAllwrapper() did return true, instead of continuing...
* Change: In Kite & Etesian, adds a setViewer() method (exported in Python)
to use the graphical ExceptionWidget when in graphic mode.
* Bug: In Cumulus, in PadsCorona.py the check for the core vs. chip size
was not returning False when invalid.
* New: In CRL Core, in Vst driver, add a support IEEE VHDL. Inactive for
now as I don't see clearly the policy for selecting it or not.
Remove the code of the old Vst driver.
In Blif parser, check for non-existent models (incomplete or
corrupted Blif file). Found by G. Gouvine.
* New: Added extras file for IDE-like support under Emacs.
* Bug: In Hurricane, in NetAlias, bad Record construction of the _next
field.
* New: In CRL Core, in VstDriver complete replacement of the old Vst
driver. Needed cleaner architecture to manage correctly files
importeds through the Blif parser, which are Verilog like.
It is build as an extension trough property and is not kept
in sync with the Cell. So it's use should be transient only.
* Change: In CRL Core, in NamingScheme forgot to change '.' (dot)
forbidden character into '_'.
* Change: In Cumulus, in the RSave plugins, remove the VHDL extensions
after saving.
* New: In Hurricane, In Cell, add Placed and Routed flags to know the
state of the Cell.
* Change: In CRL Core, In ApDriver, do not save the RoutingPads as
external connectors if the design is *not* routed (create
conflics on reload with the newly generated RoutingPads).
* Change: In Etesian, set the Placed flag on the Cell.
* Change: In Kite, set the Routed flag on the Cell.
* Change: In Cumulus, in RSavePluginAll, save the layout only if it
has a bounding box.
* New: In Hurricane, In Net & Cell, support for Net aliases names.
Use a structure based on a simple ring of NetAliasHook. The Net
holds a global map, sorted by names of all the aliases of all Nets.
Elements NetAliasesHook of the map are slaves of ring whose master
is an attribute of the Net (it is *not* in the map, as the primary
name of the Net).
In case of merge, the aliases of both Nets are merged and the
name of the merged one become an alias.
The Cell::getNet() looks in both the Net map and the aliases to
find a Net by name.
* Bug: In CRL Core, in coriolisInit.py, reoder the loading of the
configuration files so the real technology is read as early as
possible to set up the <gridsPerLambda> factor before any lambda
is actually computed...
* Bug: In CRL Core, in AcmSigda, do not try to fed the file when it
has failed to be opened. Throw a clean exception instead.
* New: In CRL Core, in Toolbox, add a NamingScheme object to convert
a design into VHDL compliant names (mainly from Blif/Verilog).
This is extensible in any case.
* New: In CRL Core, in BlifParser, slightly more informative warning
messages. Align the loading progress information on the other
parsers.
Add a capability to select which component of the design will
be returned, if there are more than one. Use the "." as separator.
For exemple you can request "Processor.Alu", which will load
the "Alu" component from the design in "Processor.blif".
To be able to save a Blif loaded design, systematically convert
all the name for VHDL compliance, as it is the format used by
the Coriolis native files (vst).
Export the Blif parser to the Python interface.
* New: In Kite, In NegociateWindow, add a counter of the number of
remaining events. Gives an idea of the ETA...
* New: In Unicorn, in cgt.by, add an option to load a Blif design from
the command line.
* New: In Cumulus, new RSave plugin to save both netlist & layout.
Partly redundant with the previous one. Have to better organize
that later.
Jean-Paul Chaput