riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Manage all devices in karakaze/AnalogDesign.readParameters(). 

* Change: In Karakaze/analogdesign/AnalogDesign.readParameters(),
    only Transistor and Capacitors where manageds. So when a devices in
    the dspec was from another type, it did issue an error.
      Now cleanly skip unsupported (yet) devices.
This commit is contained in:
Jean-Paul Chaput 2020-05-10 11:47:30 +02:00
parent b553aae8ad
commit faef4b182f
1 changed files with 27 additions and 21 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

48
karakaze/python/analogdesign.py
View File

@ -357,27 +357,33 @@ class AnalogDesign ( object ):
self.parameters.read( path ); self.parameters.read( path );
for dspec in self.devicesSpecs: for dspec in self.devicesSpecs:
if dspec[0] == MultiCapacitor: if issubclass(dspec[0],TransistorFamily):
Cname = dspec[1] Tname = dspec[1].split('_')[0]
Cparameters = self.parameters.getCapacitor( Cname ) Tparameters = self.parameters.getTransistor( Tname )
if not Cparameters: if not Tparameters:
raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for capacity \"%s\".' % Cname ] ) raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for \"%s\".' % Tname ] )
continue continue
dspec[4] = Cparameters.C * 1e+12 dspec[4] = toLength( Tparameters.W )
trace( 110, '\t- \"%s\" : C:%fpF\n' % (Cname ,dspec[4]) ) dspec[5] = toLength( Tparameters.L )
else: dspec[6] = Tparameters.M
Tname = dspec[1].split('_')[0] trace( 110, '\t- \"%s\" : W:%f L:%f M:%d\n' % (Tname
Tparameters = self.parameters.getTransistor( Tname ) ,dspec[4]
if not Tparameters: ,dspec[5]
raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for \"%s\".' % Tname ] ) ,dspec[6]) )
continue elif issubclass(dspec[0],CapacitorFamily):
dspec[4] = toLength( Tparameters.W ) Cname = dspec[1]
dspec[5] = toLength( Tparameters.L ) Cparameters = self.parameters.getCapacitor( Cname )
dspec[6] = Tparameters.M if not Cparameters:
trace( 110, '\t- \"%s\" : W:%f L:%f M:%d\n' % (Tname raise Error( 3, [ 'AnalogDesign.readParameters(): Missing parameters for capacity \"%s\".' % Cname ] )
,dspec[4] continue
,dspec[5] dspec[4] = Cparameters.C * 1e+12
,dspec[6]) ) trace( 110, '\t- \"%s\" : C:%fpF\n' % (Cname ,dspec[4]) )
elif issubclass(dspec[0],ResistorFamily):
print WarningMessage( 'Resistor devices are not supported yet by Oceane parser (instance:"{}").'.format(dspec[1]) )
elif dspec[0] == Cell:
pass
else:
print WarningMessage( 'Unsupported analog device type {0} (instance:"{1}").'.format(dspec[0],dspec[1]) )
trace( 110, '-,' ) trace( 110, '-,' )
return return