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coriolis
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Fix net creation/lookup ordering in cumulus/core2chip (fuse vss & iovss).

This commit is contained in:
Jean-Paul Chaput 2021-04-28 14:24:47 +02:00
parent 89a45180c1
commit e2d0188543
2 changed files with 11 additions and 7 deletions
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4
cumulus/src/plugins/alpha/core2chip/libresocio.py
View File

@ -117,7 +117,9 @@ class CoreToChip ( BaseCoreToChip ):
chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName ) chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName )
chipNet.setExternal( True ) chipNet.setExternal( True )
chipNet.setType ( Net.Type.GROUND ) chipNet.setType ( Net.Type.GROUND )
self.icorona.getPlug( coronaNet ).setNet( chipNet ) coronaPlug = self.icorona.getPlug( coronaNet )
if not coronaPlug.getNet():
coronaPlug.setNet( chipNet )
self.ringNetNames['vss'] = chipNet self.ringNetNames['vss'] = chipNet
ioPadConf.pads.append( Instance.create( self.chip ioPadConf.pads.append( Instance.create( self.chip
, 'p_vss_{}'.format(ioPadConf.index) , 'p_vss_{}'.format(ioPadConf.index)

4
cumulus/src/plugins/alpha/core2chip/niolib.py
View File

@ -82,7 +82,9 @@ class CoreToChip ( BaseCoreToChip ):
chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName ) chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName )
chipNet.setExternal( True ) chipNet.setExternal( True )
chipNet.setType ( Net.Type.GROUND ) chipNet.setType ( Net.Type.GROUND )
self.icorona.getPlug( coronaNet ).setNet( chipNet ) coronaPlug = self.icorona.getPlug( coronaNet )
if not coronaPlug.getNet():
coronaPlug.setNet( chipNet )
self.ringNetNames['vss'] = chipNet self.ringNetNames['vss'] = chipNet
ioPadConf.pads.append( Instance.create( self.chip ioPadConf.pads.append( Instance.create( self.chip
, 'p_vss_{}'.format(ioPadConf.index) , 'p_vss_{}'.format(ioPadConf.index)