From e2d01885437ef5a8f7d5c7e1081a0ea13921d085 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Wed, 28 Apr 2021 14:24:47 +0200 Subject: [PATCH] Fix net creation/lookup ordering in cumulus/core2chip (fuse vss & iovss). --- cumulus/src/plugins/alpha/core2chip/libresocio.py | 8 +++++--- cumulus/src/plugins/alpha/core2chip/niolib.py | 10 ++++++---- 2 files changed, 11 insertions(+), 7 deletions(-) diff --git a/cumulus/src/plugins/alpha/core2chip/libresocio.py b/cumulus/src/plugins/alpha/core2chip/libresocio.py index 119b2357..44cb67ec 100644 --- a/cumulus/src/plugins/alpha/core2chip/libresocio.py +++ b/cumulus/src/plugins/alpha/core2chip/libresocio.py @@ -117,8 +117,10 @@ class CoreToChip ( BaseCoreToChip ): chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName ) chipNet.setExternal( True ) chipNet.setType ( Net.Type.GROUND ) - self.icorona.getPlug( coronaNet ).setNet( chipNet ) - self.ringNetNames['vss'] = chipNet + coronaPlug = self.icorona.getPlug( coronaNet ) + if not coronaPlug.getNet(): + coronaPlug.setNet( chipNet ) + self.ringNetNames['vss'] = chipNet ioPadConf.pads.append( Instance.create( self.chip , 'p_vss_{}'.format(ioPadConf.index) , self.getCell(self.ioPadNames['vss']) ) ) @@ -132,7 +134,7 @@ class CoreToChip ( BaseCoreToChip ): padNet = Net.create( self.chip, ioPadConf.padSupplyNetName ) padNet.setExternal( True ) padNet.setType ( Net.Type.GROUND ) - self.ringNetNames['iovss'] = padNet + self.ringNetNames['iovss'] = padNet ioPadConf.pads.append( Instance.create( self.chip , 'p_iovss_{}'.format(ioPadConf.index) , self.getCell(self.ioPadNames['iovss']) ) ) diff --git a/cumulus/src/plugins/alpha/core2chip/niolib.py b/cumulus/src/plugins/alpha/core2chip/niolib.py index 9ecde7b2..11b445c6 100644 --- a/cumulus/src/plugins/alpha/core2chip/niolib.py +++ b/cumulus/src/plugins/alpha/core2chip/niolib.py @@ -82,8 +82,10 @@ class CoreToChip ( BaseCoreToChip ): chipNet = Net.create( self.chip, ioPadConf.coreSupplyNetName ) chipNet.setExternal( True ) chipNet.setType ( Net.Type.GROUND ) - self.icorona.getPlug( coronaNet ).setNet( chipNet ) - self.ringNetNames['vss'] = chipNet + coronaPlug = self.icorona.getPlug( coronaNet ) + if not coronaPlug.getNet(): + coronaPlug.setNet( chipNet ) + self.ringNetNames['vss'] = chipNet ioPadConf.pads.append( Instance.create( self.chip , 'p_vss_{}'.format(ioPadConf.index) , self.getCell('vss') ) ) @@ -92,12 +94,12 @@ class CoreToChip ( BaseCoreToChip ): self.chipPads += ioPadConf.pads def _buildIoGroundPads ( self, ioPadConf ): - padNet = self.chip.getNet( ioPadConf.padSupplyNetName ) + padNet = self.chip.getNet( ioPadConf.padSupplyNetName ) if not padNet: padNet = Net.create( self.chip, ioPadConf.padSupplyNetName ) padNet.setExternal( True ) padNet.setType ( Net.Type.GROUND ) - self.ringNetNames['iovss'] = padNet + self.ringNetNames['iovss'] = padNet ioPadConf.pads.append( Instance.create( self.chip , 'p_iovss_{}'.format(ioPadConf.index) , self.getCell('iovss') ) )