Fixes bad VHDL port map assignment for vectors in VST driver.

* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
    1. Bad condition for the use of VstUseConcat. Must be used *only*
       when there is more than *one* mapped name.
    2. Missing case, when there is exactly *one* mapped name, that
       means that we have one full width vector to vector assignement.
       There may be another weakness here, for the portmap we assumes
       that both vector are mapped in the *same* direction (which is
       "downto" by our convention).
    3. In the "bit by bit mapping case" (every bits of the vector are
       differents bits), use the "signal + bit index" name instead of
       juste the signal name (i.e. full width).
    Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
    we can avoid the YOSYS_FLATTEN.

crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp

@@ -222,7 +222,13 @@ namespace Vhdl {
       }
     }
 
-    if ( (mappedNames.size() == 1) or (_flags & Entity::VstUseConcat) ) {
+    if (mappedNames.size() == 1) {
+      out << setw(width) << left << _signal->getName()
+          << " => " << mappedNames[0];
+      return;
+    }
+  
+    if ( (mappedNames.size() > 1) and (_flags & Entity::VstUseConcat) ) {
       out << setw(width) << left << _signal->getName() << " => ";
   
       size_t lhsWidth  = 90 - tab.getWidth() - width - 4;
@@ -241,7 +247,9 @@ namespace Vhdl {
         out << name;
         first = false;
       }
-    } else {
+      return;
+    }
+
     const Bit* bit  = NULL;
     string     name = "UNCONNECTED";
 
@@ -252,7 +260,7 @@ namespace Vhdl {
     bool first = true;
     for ( ; imapping!=_mapping.rend() ; ++imapping ) {
       bit  = imapping ->second;
-        name = (bit) ? bit ->getSignal()->getName() : "UNCONNECTED";
+      name = (bit) ? bit->getName() : "UNCONNECTED";
 
       if (not first) out << "\n" << tab << "         , ";
       
@@ -261,7 +269,6 @@ namespace Vhdl {
       first = false;
     }
   }
-  }
 
 
 }  // Vhdl namespace.