From b48f9b40b8b7c97979c5a26b9022e28dd9e199c9 Mon Sep 17 00:00:00 2001
From: Jean-Paul Chaput <Jean-Paul.Chaput@lip6.fr>
Date: Fri, 26 Jun 2020 17:13:18 +0200
Subject: [PATCH] Fixes bad VHDL port map assignment for vectors in VST driver.

* Bug: In CRL/Vhdl::VectorPortMap::toVhdlPortMap(), two problems:
    1. Bad condition for the use of VstUseConcat. Must be used *only*
       when there is more than *one* mapped name.
    2. Missing case, when there is exactly *one* mapped name, that
       means that we have one full width vector to vector assignement.
       There may be another weakness here, for the portmap we assumes
       that both vector are mapped in the *same* direction (which is
       "downto" by our convention).
    3. In the "bit by bit mapping case" (every bits of the vector are
       differents bits), use the "signal + bit index" name instead of
       juste the signal name (i.e. full width).
    Solves the Libre-SOC/soclayout/experiment6/fpmul64 problem, now
    we can avoid the YOSYS_FLATTEN.
---
 .../src/ccore/alliance/vst/VhdlPortMap.cpp    | 57 +++++++++++--------
 1 file changed, 32 insertions(+), 25 deletions(-)

diff --git a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
index 2cd91314..13a5d54d 100644
--- a/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
+++ b/crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
@@ -155,14 +155,14 @@ namespace Vhdl {
   {
     vector<string>  mappedNames;
     if (getSignal()->isContiguous()) {
-      int             begin  = -1;
-      int             end    = -1;
-      int             delta  =  0;
-      int             deltap =  0;
-      const Bit*      bit    = NULL;
-      const Bit*      bitp   = NULL;
-      string          name   = "UNCONNECTED";
-      string          namep  = "UNCONNECTED";
+      int        begin  = -1;
+      int        end    = -1;
+      int        delta  =  0;
+      int        deltap =  0;
+      const Bit* bit    = NULL;
+      const Bit* bitp   = NULL;
+      string     name   = "UNCONNECTED";
+      string     namep  = "UNCONNECTED";
   
       auto imapping  = _mapping.rbegin();
       auto imappingp = _mapping.rbegin();
@@ -221,8 +221,14 @@ namespace Vhdl {
         }
       }
     }
+
+    if (mappedNames.size() == 1) {
+      out << setw(width) << left << _signal->getName()
+          << " => " << mappedNames[0];
+      return;
+    }
   
-    if ( (mappedNames.size() == 1) or (_flags & Entity::VstUseConcat) ) {
+    if ( (mappedNames.size() > 1) and (_flags & Entity::VstUseConcat) ) {
       out << setw(width) << left << _signal->getName() << " => ";
   
       size_t lhsWidth  = 90 - tab.getWidth() - width - 4;
@@ -241,25 +247,26 @@ namespace Vhdl {
         out << name;
         first = false;
       }
-    } else {
-      const Bit* bit  = NULL;
-      string     name = "UNCONNECTED";
+      return;
+    }
 
-      // cerr << "VhdlPortMap is in bit mode for \"" << _signal->getName() << "\""
-      //      << " _flags:" << _flags << " mappedNames:" << _mapping.size() << endl;
+    const Bit* bit  = NULL;
+    string     name = "UNCONNECTED";
 
-      auto imapping  = _mapping.rbegin();
-      bool first = true;
-      for ( ; imapping!=_mapping.rend() ; ++imapping ) {
-        bit  = imapping ->second;
-        name = (bit) ? bit ->getSignal()->getName() : "UNCONNECTED";
+    // cerr << "VhdlPortMap is in bit mode for \"" << _signal->getName() << "\""
+    //      << " _flags:" << _flags << " mappedNames:" << _mapping.size() << endl;
 
-        if (not first) out << "\n" << tab << "         , ";
-        
-        out << setw(width) << left << _signal->getBit(imapping->first)->getName()
-            << " => " << name;
-        first = false;
-      }
+    auto imapping  = _mapping.rbegin();
+    bool first = true;
+    for ( ; imapping!=_mapping.rend() ; ++imapping ) {
+      bit  = imapping ->second;
+      name = (bit) ? bit->getName() : "UNCONNECTED";
+
+      if (not first) out << "\n" << tab << "         , ";
+      
+      out << setw(width) << left << _signal->getBit(imapping->first)->getName()
+          << " => " << name;
+      first = false;
     }
   }