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More detailed error message in case of VHDL PORT MAP discrepency.

This commit is contained in:
Jean-Paul Chaput 2022-05-12 17:51:30 +02:00
parent cd60032d9c
commit 921c519bd3
1 changed files with 4 additions and 4 deletions
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8
crlcore/src/ccore/alliance/vst/VstParserGrammar.yy
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@ -854,12 +854,12 @@ association_element
<< " Port map assignment discrepency " << " Port map assignment discrepency "
<< "instance:" << Vst::states->_instanceNets.size() << "instance:" << Vst::states->_instanceNets.size()
<< " vs. model:" << Vst::states->_masterNets.size(); << " vs. model:" << Vst::states->_masterNets.size();
message << "\nModel:"; message << "\nModel \"" << Vst::states->_instance->getMasterCell()->getName() << "\":";
for ( Net* net : Vst::states->_masterNets ) for ( Net* net : Vst::states->_masterNets )
message << " \"" << net->getName() << "\""; message << "\n* \"" << net->getName() << "\"";
message << "\nInstance:"; message << "\nInstance " << Vst::states->_instance->getName() << "\":";
for ( Net* net : Vst::states->_instanceNets ) for ( Net* net : Vst::states->_instanceNets )
message << " \"" << net->getName() << "\""; message << "\n* \"" << net->getName() << "\"";
throw Error( message.str() ); throw Error( message.str() );
} }