From 921c519bd3568b98081b436683d33d86170a8176 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Thu, 12 May 2022 17:51:30 +0200 Subject: [PATCH] More detailed error message in case of VHDL PORT MAP discrepency. --- crlcore/src/ccore/alliance/vst/VstParserGrammar.yy | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy b/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy index f50cde8d..baf862fe 100644 --- a/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy +++ b/crlcore/src/ccore/alliance/vst/VstParserGrammar.yy @@ -854,12 +854,12 @@ association_element << " Port map assignment discrepency " << "instance:" << Vst::states->_instanceNets.size() << " vs. model:" << Vst::states->_masterNets.size(); - message << "\nModel:"; + message << "\nModel \"" << Vst::states->_instance->getMasterCell()->getName() << "\":"; for ( Net* net : Vst::states->_masterNets ) - message << " \"" << net->getName() << "\""; - message << "\nInstance:"; + message << "\n* \"" << net->getName() << "\""; + message << "\nInstance " << Vst::states->_instance->getName() << "\":"; for ( Net* net : Vst::states->_instanceNets ) - message << " \"" << net->getName() << "\""; + message << "\n* \"" << net->getName() << "\""; throw Error( message.str() ); }