Add core2chip file for gf180mcu
This is a copy of the sky130 one.
This commit is contained in:
Staf Verhaegen
parent
1262f65eec
commit
7b04a76fae
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@ -74,6 +74,7 @@
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/alpha/core2chip/niolib.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/alpha/core2chip/libresocio.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/alpha/core2chip/sky130.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/alpha/core2chip/gf180mcu.py
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)
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set ( pyPluginAlphaChip ${CMAKE_CURRENT_SOURCE_DIR}/plugins/alpha/chip/__init__.py
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${CMAKE_CURRENT_SOURCE_DIR}/plugins/alpha/chip/configuration.py
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@ -0,0 +1,294 @@
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# This file is part of the Coriolis Software.
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# Copyright (c) Sorbonne Université 2020-2021, All Rights Reserved
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#
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# +-----------------------------------------------------------------+
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# | C O R I O L I S |
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# | C u m u l u s - P y t h o n T o o l s |
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# | |
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# | Author : Jean-Paul CHAPUT |
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# | E-mail : Jean-Paul.Chaput@lip6.fr |
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# | =============================================================== |
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# | Python : "./plugins/core2chip/sky130.py" |
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# +-----------------------------------------------------------------+
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"""
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Core2Chip configuration for the Sky130 harness.
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"""
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import sys
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import re
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from Hurricane import DbU, DataBase, UpdateSession, Breakpoint, \
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Transformation , Box, Instance , Net, \
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Contact
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import Viewer
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from CRL import Catalog
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from CRL import AllianceFramework, DefImport
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from helpers import trace, l, u, n
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from helpers.io import ErrorMessage, WarningMessage
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from helpers.overlay import CfgCache, UpdateSession
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import plugins.alpha.chip
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from plugins.alpha.block.configuration import IoPin, GaugeConf
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from plugins.alpha.core2chip.core2chip import CoreToChip as BaseCoreToChip, \
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IoNet, IoPad
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# -------------------------------------------------------------------
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# Class : "MatchHarnessIos".
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class MatchHarnessIos ( object ):
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"""
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In case the connections of the core to the I/O pins are not specified
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(empty ioPadsSpecs list), try to guess the connection by names.
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.. note:: Currently, only matching with the (io_in,io_out,io_oeb),
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power and clock are supported.
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"""
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def __init__ ( self, coreToChip ):
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self.coreToChip = coreToChip
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self.digitalIos = []
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for i in range(38):
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self.digitalIos.append( [None, None, None] )
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self.clock = None
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self.digitalVdd = None
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self.digitalVss = None
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@property
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def conf ( self ): return self.coreToChip.conf
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def matchCore ( self ):
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print( ' o Using implicit Caravel harness connections.' )
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reIoIn = re.compile( r'^(?P<name>\w+)\((?P<index>\d+)\)$' )
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for net in self.conf.core.getNets():
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if not net.isExternal(): continue
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if net.isClock():
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self.clock = net
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continue
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if net.isPower():
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self.digitalVdd = net
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continue
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if net.isGround():
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self.digitalVss = net
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continue
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m = reIoIn.match( net.getName() )
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if m:
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index = int( m.group('index') )
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if index >= 38:
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continue
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if m.group('name') == 'io_in':
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self.digitalIos[ index ][0] = net
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elif m.group('name') == 'io_out':
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self.digitalIos[ index ][1] = net
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elif m.group('name') == 'io_oeb':
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self.digitalIos[ index ][2] = net
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else:
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print( WarningMessage('Unable to match "{}" into harness net.'.format( net.getName() )))
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else:
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print( WarningMessage('Unable to match "{}" into harness net.'.format( net.getName() )))
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if self.digitalVdd:
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self.conf.chipConf.addIoPad( (None, None, 'power_0', 'vccd1', self.digitalVdd.getName()), 0 )
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else:
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print( WarningMessage('Missing digital power net in "{}".'.format(self.conf.core.getName())) )
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if self.digitalVss:
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self.conf.chipConf.addIoPad( (None, None, 'ground_0', 'vssd1', self.digitalVss.getName()), 0 )
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else:
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print( WarningMessage('Missing digital ground net in "{}".'.format(self.conf.core.getName())) )
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if self.clock:
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self.conf.chipConf.addIoPad( (None, None, None, 'user_clock2', self.clock.getName()), 0 )
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else:
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print( WarningMessage('Missing digital clock net in "{}".'.format(self.conf.core.getName())) )
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for i in range(38):
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ioNets = self.digitalIos[ i ]
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if ioNets[0] and ioNets[1] and ioNets[2]:
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self.conf.chipConf.addIoPad( ( None, None, None, ioNets[0].getName()
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, ioNets[0].getName()
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, ioNets[1].getName()
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, ioNets[2].getName() ), 0 )
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elif ioNets[0] and not ioNets[1] and not ioNets[2]:
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self.conf.chipConf.addIoPad( ( None, None, None, ioNets[0].getName()
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, ioNets[0].getName() ), 0 )
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elif not ioNets[0] and not ioNets[1] and ioNets[2]:
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self.conf.chipConf.addIoPad( ( None, None, None, ioNets[2].getName()
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, ioNets[2].getName() ), 0 )
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elif not ioNets[0] and not ioNets[1] and not ioNets[2]:
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continue
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else:
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print( WarningMessage( [ 'Incomplete digital connexion to I/O pad "{}".'.format(index)
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, '* In :{}'.format( ioNets[0] )
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, '* Out:{}'.format( ioNets[1] )
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, '* OEb:{}'.format( ioNets[2] ) ]))
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# --------------------------------------------------------------------
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# Class : "sky130.CoreToChip"
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class CoreToChip ( BaseCoreToChip ):
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"""
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Provide harness-specific part for SkyWater 130 (works in real mode).
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Emulate the behavior of I/O pads.
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"""
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rePadType = re.compile(r'(?P<type>.+)_(?P<index>[\d]+)$')
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def __init__ ( self, core ):
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self.ioPadNames = { 'bidir' :'IOHarnessInOut'
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, 'analog':'IOHarnessAnalog'
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, 'vdd' :'IOHarnessVdd'
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, 'vss' :'IOHarnessVss'
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, 'iovdd' :'IOHarnessIOVdd'
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, 'iovss' :'IOHarnessIOVss'
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}
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BaseCoreToChip.__init__ ( self, core )
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self.conf.useHarness = True
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self.ringNetNames = { 'vssa2' : None
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, 'vdda2' : None
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, 'vssa1' : None
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, 'vdda1' : None
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, 'vssd2' : None
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, 'vccd2' : None
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, 'vssd1' : None
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, 'vccd1' : None
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}
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self.ioPadInfos = [ BaseCoreToChip.IoPadInfo( IoPad.BIDIR
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, self.ioPadNames['bidir']
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, 'pad', ['io_in', 'io_out', 'io_oeb'] )
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, BaseCoreToChip.IoPadInfo( IoPad.ANALOG
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, self.ioPadNames['analog']
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, 'pad', ['pad', 'padres'] )
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]
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self._getPadLib()
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if self.conf.chipConf.ioPadsCount() == 0:
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MatchHarnessIos( self ).matchCore()
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return
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def _getPadLib ( self ):
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return None
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def getNetType ( self, netName ):
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if netName.startswith('vss') or netName.startswith('vee'): return Net.Type.GROUND
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if netName.startswith('vdd') or netName.startswith('vcc'): return Net.Type.POWER
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return Net.Type.LOGICAL
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def isGlobal ( self, netName ):
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if netName in self.ringNetNames: return True
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return False
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def getCell ( self, masterCellName ):
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raise NotImplementedError( 'coreToChip.getCell(): Harness does not provides I/O pad cells.' )
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def _buildCoreGroundPads ( self, ioPadConf ):
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trace( 550, '\tsky130.CoreToChip._buildGroundPowerPads()\n' )
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coreNet = self.core .getNet( ioPadConf.coreSupplyNetName )
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coronaNet = self.corona.getNet( ioPadConf.coreSupplyNetName )
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chipNet = self.chip .getNet( ioPadConf.padSupplyNetName )
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if not coronaNet:
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coronaNet = Net.create( self.corona, ioPadConf.coreSupplyNetName )
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coronaNet.setExternal ( True )
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coronaNet.setGlobal ( True )
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coronaNet.setDirection( Net.Direction.IN )
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coronaNet.setType ( Net.Type.GROUND )
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self.icore.getPlug( coreNet ).setNet( coronaNet )
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trace( 550, '\tCreated corona ground net: {}\n'.format(coronaNet) )
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if not chipNet:
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raise ErrorMessage( 1, 'Harness do not provide ground net ""{}' \
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.format( ioPadConf.padSupplyNetName ))
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coronaPlug = self.icorona.getPlug( coronaNet )
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if not coronaPlug.getNet():
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coronaPlug.setNet( chipNet )
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self.groundPadCount += 1
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def _buildCorePowerPads ( self, ioPadConf ):
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trace( 550, '\tsky130.CoreToChip._buildCorePowerPads()\n' )
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coreNet = self.core .getNet( ioPadConf.coreSupplyNetName )
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coronaNet = self.corona.getNet( ioPadConf.coreSupplyNetName )
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chipNet = self.chip .getNet( ioPadConf.padSupplyNetName )
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if not coronaNet:
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coronaNet = Net.create( self.corona, ioPadConf.coreSupplyNetName )
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coronaNet.setExternal ( True )
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coronaNet.setGlobal ( True )
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coronaNet.setDirection( Net.Direction.IN )
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coronaNet.setType ( Net.Type.POWER )
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self.icore.getPlug( coreNet ).setNet( coronaNet )
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trace( 550, '\tCreated corona power net: {}\n'.format(coronaNet) )
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if not chipNet:
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raise ErrorMessage( 1, 'Harness do not provide power net ""{}' \
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.format( ioPadConf.padSupplyNetName ))
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self.icorona.getPlug( coronaNet ).setNet( chipNet )
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coronaPlug = self.icorona.getPlug( coronaNet )
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if not coronaPlug.getNet():
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coronaPlug.setNet( chipNet )
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self.powerPadCount += 1
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def _buildClockPads ( self, ioPadConf ):
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"""For "Sky130" there is no specialized clock I/O pad. So do nothing."""
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pass
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def _connectClocks ( self ):
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"""For "Sky130" there is no pad internal clock ring. So do nothing."""
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pass
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def _loadHarness ( self ):
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"""
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Load the DEF file containing the reference harness layout.
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Remove the supplied internal power grid and slightly shrink
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the central P&R area so that I/O pins are fully outside of it.
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"""
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self.harness = DefImport.load( self.conf.cfg.harness.path )
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innerAb = self.harness.getAbutmentBox()
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wholeBb = self.harness.getBoundingBox()
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filterBb = Box( wholeBb.getXMin(), innerAb.getYMin()
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, wholeBb.getXMax(), innerAb.getYMax() )
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components = []
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for component in self.harness.getComponentsUnder( filterBb ):
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if component.getNet().isSupply() and filterBb.contains( component.getBoundingBox() ):
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components.append( component )
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for instance in self.harness.getInstancesUnder( filterBb ):
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components.append( instance )
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with UpdateSession():
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for component in components:
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component.destroy()
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components = []
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filterBb = Box( innerAb.getXMin(), wholeBb.getYMin()
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, innerAb.getXMax(), wholeBb.getYMax() )
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for component in self.harness.getComponentsUnder( filterBb ):
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if component.getNet().isSupply() and filterBb.contains( component.getBoundingBox() ):
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components.append( component )
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for instance in self.harness.getInstancesUnder( filterBb ):
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components.append( instance )
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with UpdateSession():
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for component in components:
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component.destroy()
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areaXMin = innerAb.getXMin()
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areaYMin = innerAb.getYMin()
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areaXMax = innerAb.getXMax()
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areaYMax = innerAb.getYMax()
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for net in self.harness.getNets():
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if net.isSupply(): continue
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for component in net.getComponents():
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trace( 550, '\t| {}\n'.format(component) )
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bb = component.getBoundingBox()
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side = None
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if bb.getXMin() < innerAb.getXMin():
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areaXMin = max( areaXMin, bb.getXMax() )
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side = IoPin.WEST
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if bb.getXMax() > innerAb.getXMax():
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areaXMax = min( areaXMax, bb.getXMin() )
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side = IoPin.EAST
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if bb.getYMin() < innerAb.getYMin():
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areaYMin = max( areaYMin, bb.getYMax() )
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side = IoPin.SOUTH
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if bb.getYMax() > innerAb.getYMax():
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areaYMax = min( areaYMax, bb.getYMin() )
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side = IoPin.NORTH
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trace( 550, '\tside: {} {}\n'.format(side,type(component)) )
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if side and isinstance(component,Contact):
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trace( 550, '\tAdded on {} side: {}\n'.format(side,component) )
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self.conf.chipConf.addHarnessPin( component, side )
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area = Box( areaXMin, areaYMin, areaXMax, areaYMax )
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area.inflate( - self.conf.hRoutingGauge.getPitch()*2
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, - self.conf.vRoutingGauge.getPitch()*2 )
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xmodulo = area.getWidth () % self.conf.sliceStep
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ymodulo = area.getHeight() % self.conf.sliceHeight
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area.inflate( 0, 0, -xmodulo, -ymodulo )
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self.harness.setAbutmentBox( area )
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return self.harness
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