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Bug in VHDL portmap. Too strict checking in Kite & Etesian ::setViewer(). 

* Bug: In CRL Core, in VectorPortMap::VhdlPortMap(), if the connection
    was made to *non-contiguous* bits of an otherwise *contiguous* vector,
    it was using a span instead of the separate bits. Now check that
    bits are contiguous (delta: +1/-1) and the delta do not change of
    sign.
* Change: In Etesian & Kite, the Python interface function ::setViewer()
    was checking that the argument was indeed a CellViewer, but in text
    mode it is None. Now, silently ignore the argument if it cannot be
    converted into CellViewer.
This commit is contained in:
Jean-Paul Chaput 2015-06-08 12:01:32 +02:00
parent 51043df640
commit 701487247d
3 changed files with 31 additions and 17 deletions
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14
crlcore/src/ccore/alliance/vst/VhdlPortMap.cpp
View File

@ -157,6 +157,8 @@ namespace Vhdl {
vector<string> mappedNames;
int begin = -1;
int end = -1;
int delta = 0;
int deltap = 0;
const Bit* bit = NULL;
const Bit* bitp = NULL;
string name = "UNCONNECTED";
@ -176,15 +178,19 @@ namespace Vhdl {
and bitp->getSignal()->isVector()
and bitp->getSignal()->isContiguous()
and (name == namep)) {
if (begin < 0) begin = bitp->getIndex();
if (end < 0) end = bit ->getIndex();
delta = (int)bit->getIndex() - (int)bitp->getIndex();
int delta = (int)bit->getIndex() - (int)bitp->getIndex();
if ( not ((delta > 0) xor (begin < end)) ) {
if (begin < 0) begin = bitp->getIndex();
if (end < 0) end = bitp->getIndex();
if (deltap == 0) deltap = delta;
if ( (delta == deltap) and ((delta == -1) or (delta == +1)) ) {
end = bit->getIndex();
deltap = delta;
continue;
}
}
delta = 0;
if (begin != end) {
string vdir = (begin < end) ? "to" : "downto";

8
etesian/src/PyEtesianEngine.cpp
View File

@ -49,6 +49,7 @@ namespace Etesian {
using Isobar::PyCell;
using Isobar::PyCell_Link;
using Isobar::PyCellViewer;
using Isobar::PyTypeCellViewer;
using CRL::PyToolEngine;
@ -112,11 +113,14 @@ extern "C" {
HTRY
METHOD_HEAD( "EtesianEngine.setViewer()" )
PyCellViewer* pyViewer;
if (not ParseOneArg("EtesianEngine.setViewer()",args,":cellView",(PyObject**)&pyViewer)) {
PyObject* pyViewer = NULL;
if (not PyArg_ParseTuple(args,"O:EtesianEngine.setViewer()",&pyViewer)) {
PyErr_SetString( ConstructorError, "Bad parameters given to EtesianEngine.setViewer()." );
return NULL;
}
if (IsPyCellViewer(pyViewer)) {
etesian->setViewer( PYCELLVIEWER_O(pyViewer) );
}
HCATCH
Py_RETURN_NONE;

10
kite/src/PyKiteEngine.cpp
View File

@ -1,7 +1,7 @@
// -*- C++ -*-
//
// This file is part of the Coriolis Software.
// Copyright (c) UPMC/LIP6 2010-2015, All Rights Reserved
// Copyright (c) UPMC 2010-2015, All Rights Reserved
//
// +-----------------------------------------------------------------+
// | C O R I O L I S |
@ -49,6 +49,7 @@ namespace Kite {
using Isobar::PyCell;
using Isobar::PyCell_Link;
using Isobar::PyCellViewer;
using Isobar::PyTypeCellViewer;
using CRL::PyToolEngine;
@ -131,11 +132,14 @@ extern "C" {
HTRY
METHOD_HEAD( "KiteEngine.setViewer()" )
PyCellViewer* pyViewer;
if (not ParseOneArg("KiteEngine.setViewer()",args,":cellView",(PyObject**)&pyViewer)) {
PyObject* pyViewer = NULL;
if (not PyArg_ParseTuple(args,"O:EtesianEngine.setViewer()",&pyViewer)) {
PyErr_SetString( ConstructorError, "Bad parameters given to EtesianEngine.setViewer()." );
return NULL;
}
if (IsPyCellViewer(pyViewer)) {
kite->setViewer( PYCELLVIEWER_O(pyViewer) );
}
HCATCH
Py_RETURN_NONE;