riscv
/
coriolis
mirror of https://gitlab.lip6.fr/vlsi-eda/coriolis.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Correct edge capacity display in debug mode.

This commit is contained in:
Jean-Paul Chaput 2014-08-03 16:38:57 +02:00
parent fbeef95c0f
commit 6588902780
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
kite/src/KiteEngine.cpp
View File

@ -340,7 +340,7 @@ namespace Kite {
size_t capacity = (edge->getCapacity()>edgeReserved) size_t capacity = (edge->getCapacity()>edgeReserved)
? (edge->getCapacity()-edgeReserved) : 0; ? (edge->getCapacity()-edgeReserved) : 0;
//cerr << "Appling capacity percentage " << (edgePercent*100.0) << "% (" //cerr << "Setting capacity " << capacity << " ("
// << capacity << ") on: " << edge << endl; // << capacity << ") on: " << edge << endl;
edge->setCapacity( capacity ); edge->setCapacity( capacity );
} }