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Mangle the "'" in Verilog to VHDL translator.

This commit is contained in:
Jean-Paul Chaput 2022-05-12 17:52:22 +02:00
parent 0a64f3b83d
commit 59c0ab067b
1 changed files with 10 additions and 9 deletions
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1
crlcore/src/ccore/toolbox/NamingScheme.cpp
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@ -94,6 +94,7 @@ namespace CRL {
if (translated == '%' ) translated = '_';
if (translated == '$' ) translated = '_';
if (translated == '?' ) translated = '_';
if (translated == '\'' ) translated = '_';
if (translated == ':' ) translated = '_';
if (translated == '[' ) translated = leftPar;
if (translated == ']' ) translated = rightPar;