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Better Verilog/VHDL name mixing in the Blif parser. 

* Change: In Model::connectSubckts(), when trying to lookup the
    Hurricane Net from it's Blif name, try first as a VHDL one then
    after a Verilog to VHDL translation. Especially useful for bits
    of vectorized names ("signal[X]" --> "signal(X)").
This commit is contained in:
Jean-Paul Chaput 2021-02-01 16:18:25 +01:00
parent 48357c37a9
commit 2ba7bb4fca
1 changed files with 12 additions and 7 deletions
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5
crlcore/src/ccore/blif/BlifParser.cpp
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@ -46,6 +46,7 @@ using namespace CRL;
namespace { namespace {
using namespace std; using namespace std;
using CRL::NamingScheme;
//inline bool isAbcAutomaticName ( string name ) //inline bool isAbcAutomaticName ( string name )
@ -681,6 +682,9 @@ namespace {
// << endl; // << endl;
Net* net = _cell->getNet( netName ); Net* net = _cell->getNet( netName );
Net* masterNet = instance->getMasterCell()->getNet(masterNetName); Net* masterNet = instance->getMasterCell()->getNet(masterNetName);
if(not masterNet) {
Name vlogMasterNetName = NamingScheme::vlogToVhdl( masterNetName, NamingScheme::NoLowerCase );
masterNet = instance->getMasterCell()->getNet(vlogMasterNetName);
if(not masterNet) { if(not masterNet) {
ostringstream tmes; ostringstream tmes;
tmes << "The master net <" << masterNetName << "> hasn't been found " tmes << "The master net <" << masterNetName << "> hasn't been found "
@ -690,6 +694,7 @@ namespace {
<< endl; << endl;
throw Error(tmes.str()); throw Error(tmes.str());
} }
}
Plug* plug = instance->getPlug( masterNet ); Plug* plug = instance->getPlug( masterNet );
if(not plug) { if(not plug) {