From 2ba7bb4fca69055b926a23cf1e75cad273bdee00 Mon Sep 17 00:00:00 2001 From: Jean-Paul Chaput Date: Mon, 1 Feb 2021 16:18:25 +0100 Subject: [PATCH] Better Verilog/VHDL name mixing in the Blif parser. * Change: In Model::connectSubckts(), when trying to lookup the Hurricane Net from it's Blif name, try first as a VHDL one then after a Verilog to VHDL translation. Especially useful for bits of vectorized names ("signal[X]" --> "signal(X)"). --- crlcore/src/ccore/blif/BlifParser.cpp | 19 ++++++++++++------- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/crlcore/src/ccore/blif/BlifParser.cpp b/crlcore/src/ccore/blif/BlifParser.cpp index d073ea5b..4fa9d697 100644 --- a/crlcore/src/ccore/blif/BlifParser.cpp +++ b/crlcore/src/ccore/blif/BlifParser.cpp @@ -46,6 +46,7 @@ using namespace CRL; namespace { using namespace std; + using CRL::NamingScheme; //inline bool isAbcAutomaticName ( string name ) @@ -682,13 +683,17 @@ namespace { Net* net = _cell->getNet( netName ); Net* masterNet = instance->getMasterCell()->getNet(masterNetName); if(not masterNet) { - ostringstream tmes; - tmes << "The master net <" << masterNetName << "> hasn't been found " - << "for instance <" << subckt->getInstanceName() << "> " - << "of model <" << subckt->getModelName() << ">" - << "in model <" << getCell()->getName() << ">" - << endl; - throw Error(tmes.str()); + Name vlogMasterNetName = NamingScheme::vlogToVhdl( masterNetName, NamingScheme::NoLowerCase ); + masterNet = instance->getMasterCell()->getNet(vlogMasterNetName); + if(not masterNet) { + ostringstream tmes; + tmes << "The master net <" << masterNetName << "> hasn't been found " + << "for instance <" << subckt->getInstanceName() << "> " + << "of model <" << subckt->getModelName() << ">" + << "in model <" << getCell()->getName() << ">" + << endl; + throw Error(tmes.str()); + } } Plug* plug = instance->getPlug( masterNet );