coriolis/crlcore/etc/CMakeLists.txt

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CMake
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install ( FILES techno.conf DESTINATION ${SYS_CONF_DIR}/coriolis2 )
install ( DIRECTORY common DESTINATION ${SYS_CONF_DIR}/coriolis2 )
install ( DIRECTORY ispd05 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
install ( DIRECTORY cmos DESTINATION ${SYS_CONF_DIR}/coriolis2 )
install ( DIRECTORY vsc200 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
install ( DIRECTORY scmos_deep_018 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
Correction in plugins to support msxlib compatible pads. * New: In CRL Core, in helpers & alliance.conf, set and read a "PAD" variable to define the pad model name extension ("px" for "sxlib and "pxr" for vsxlib, this is provisional). * New: In CRL Core, in plugin.conf, add parameters to define the name of used for power & clock supply. We may remove the extention in the future (to be more coherent with the previous modification). * New: In Cumulus, in chip.Configuration.GaugeConf._rpAccess(), no longer place the accessing contact *at the center* of the RoutingPad. It works under sxlib because buffers & registers all have same size terminals. But this is not true under vsxlib, leading to misaligned contacts & wires. Now systematically place on the slice midlle track (maybe with one pitch above or below). This is still very weak as we do not check if the terminal reach were the contact is being put. Has to be strenthened in the future. * New: In Cumulus, in chip.Configuration.ChipConf, read the new clock & power pad parameters. * Change: In Isobar (and all other Python wrappers), uses PyLong instead of PyInt for DbU conversions. In PyHurricane argument converter, automatically check for both PyLong and then PyInt. * Change: In Cumulus, in chip.PadsCorona, more accurate error message in case of discrepency in global net connections (i.e. no net of the same name in instance model and instance model owner. * Change: In Kite, in BuildPowerRails, when looking up at the pads model name to find "pck_" or "pvddeck_", do not compare the extension part. But we still use hard-coded stem pad names, maybe we shouldn't. * Bug: In Katabatic, in GCellConfiguration::_do_xG_xM1_xM3(), there was a loop in the search of the best N/E initial RoutingPad. * Bug: In Kite, in KiteEngine::protectRoutingPads(), *do not* protect RoutingPads of fixed nets, they are already through the BuildPowerRails stage (and it's causing scary overlap warning messages). * Bug: In Cumulus, in ClockTree.HTreeNode.addLeaf(), do not create deep-plug when the core is flat (not sub-modules). All the new nets are at core level. * Bug: In Cumulus, in ChipPlugin.PlaceCore.doFloorplan(), ensure that the core is aligned on the GCell grid (i.e. the slice grid of the overall chip). * Bug: In Kite, in GCellTopology::_do_xG_xM1_xM3(), infinite loop while looking for the bigger N-E RoutingPad. Forgot to decrement the index...
2014-09-13 10:45:30 -05:00
install ( DIRECTORY scn6m_deep_09 DESTINATION ${SYS_CONF_DIR}/coriolis2 )
install ( DIRECTORY hcmos9gp DESTINATION ${SYS_CONF_DIR}/coriolis2 )