caravel/signoff/mgmt_protect/final_summary_report.csv

1	design	design_name	config	flow_status	total_runtime	routed_runtime	(Cell/mm^2)/Core_Util	DIEAREA_mm^2	CellPer_mm^2	OpenDP_Util	Peak_Memory_Usage_MB	cell_count	tritonRoute_violations	Short_violations	MetSpc_violations	OffGrid_violations	MinHole_violations	Other_violations	Magic_violations	antenna_violations	lvs_total_errors	cvc_total_errors	klayout_violations	wire_length	vias	wns	pl_wns	optimized_wns	fastroute_wns	spef_wns	tns	pl_tns	optimized_tns	fastroute_tns	spef_tns	HPWL	routing_layer1_pct	routing_layer2_pct	routing_layer3_pct	routing_layer4_pct	routing_layer5_pct	routing_layer6_pct	wires_count	wire_bits	public_wires_count	public_wire_bits	memories_count	memory_bits	processes_count	cells_pre_abc	AND	DFF	NAND	NOR	OR	XOR	XNOR	MUX	inputs	outputs	level	EndCaps	TapCells	Diodes	Total_Physical_Cells	CoreArea_um^2	power_slowest_internal_uW	power_slowest_switching_uW	power_slowest_leakage_uW	power_typical_internal_uW	power_typical_switching_uW	power_typical_leakage_uW	power_fastest_internal_uW	power_fastest_switching_uW	power_fastest_leakage_uW	critical_path_ns	suggested_clock_period	suggested_clock_frequency	CLOCK_PERIOD	SYNTH_STRATEGY	SYNTH_MAX_FANOUT	FP_CORE_UTIL	FP_ASPECT_RATIO	FP_PDN_VPITCH	FP_PDN_HPITCH	PL_TARGET_DENSITY	GRT_ADJUSTMENT	STD_CELL_LIBRARY	DIODE_INSERTION_STRATEGY
2	/openlane/designs/mgmt_protect	mgmt_protect	RUN_3	flow completed	0h7m19s0ms	0h1m55s0ms	-2.0	0.304	-1	3.25	1261.57	-1	0	0	0	0	0	0	9	-1	-1	-1	-1	783964	29113	-1.28	-2.11	0.0	0.0	0.0	-42.18	-104.65	0.0	0.0	0.0	747220322.0	0.0	67.42	17.31	45.23	3.7	-1	176	2014	48	1886	0	0	0	921	333	0	0	0	0	0	0	0	1088	626	2	194	4006	0	4200	277421.0688	-1	-1	-1	-1	-1	-1	-1	-1	-1	-1	8.0	125.0	8	AREA 0	10	50	1	472.190	36.720	0.11	0.05	sky130_fd_sc_hd	4