M0stafaRady f0494ef4b1 update make file to take user_project_wrapper file as input for iverilog		2022-10-02 06:48:29 -07:00
..
dv	update make file to take user_project_wrapper file as input for iverilog	2022-10-02 06:48:29 -07:00
gl	reharden!: gpio_control_block	2022-09-27 07:09:26 -07:00
rtl	Add RTL for 2 debug regs used to test and located inside user_project_wrapper	2022-09-30 03:52:34 -07:00
stubs	[DATA] Add spare_logic_block	2021-11-24 20:36:23 +02:00